IPR-CRC Altera, IPR-CRC Datasheet - Page 6

• Manufacturer Part Number: IPR-CRC
• Description: IP CORE Renewal Of IP-CRC
• Manufacturer: Altera

Specifications of IPR-CRC

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

1–2
Features
CRC Compiler User Guide
Table 1–2. Device Family Support (Part 2 of 2)
The following list summarizes the features of the CRC Compiler:
■
■
■
■
■
■
■
■
■
■
■
■
Cyclone IV GX
HardCopy
HardCopy III
HardCopy IV (E, GX)
Stratix
Stratix GX
Stratix II
Stratix II GX
Stratix III
Stratix IV
Other device families
Highly parameterized Cyclic Redundancy Check (CRC) generator and checker
CRC-32, CRC-16-ANSI, and CRC-16-CCITT generator polynomials
High-speed operation, over 250 MHz for many configurations
Configurable input datapath width from 1 to 256 bits (power-of-two)
Configurable CRC starting value
Built-in support for the following:
■
■
■
■
Avalon
message/codeword bits
Support for all possible end-of-packet byte residues
Verilog and VHDL demonstration testbenches
Easy-to-use MegaWizard
IP functional simulation models for use in Altera-supported VHDL and Verilog
HDL simulators
Support for OpenCore Plus evaluation
Inverting output data
Reversing input and output data
Partial first word
Multi-channel operation
®
®
II
Device Family
Streaming (Avalon-ST) interface without backpressure for
Preliminary
™
interface
Preliminary
Full
Preliminary
Preliminary
Full
Full
Full
Full
Full
Preliminary
No support
Support
© November 2009 Altera Corporation
Chapter 1: About This Compiler
Features