IPR-CRC Altera, IPR-CRC Datasheet - Page 18

• Manufacturer Part Number: IPR-CRC
• Description: IP CORE Renewal Of IP-CRC
• Manufacturer: Altera

Specifications of IPR-CRC

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–2
CRC Compiler User Guide
empty are ignored. Following a fixed number of clock cycles after the final word,
indicated by assertion of endofpacket, crcvalid is asserted and the computed
CRC value is available on the checksum output. The value of checksum is
undefined at other times. For the delay between assertion of endofpacket and
crcvalid, refer to the Latency panel of the MegaWizard interface.
The CRC generator can start computing the checksum of a new packet while it is
completing the calculation for the previous packet, that is before it asserts crcvalid.
The data source may assert startofpacket on the clock cycle immediately
following endofpacket, regardless of the generator's latency.
Figure 3–2
operations respectively.
Figure 3–2. Typical CRC Generator Application
Figure 3–3. CRC Generator Operation
and
Data source
checksum[7:0]
startofpacket
endofpacket
empty[3:0]
datavalid
data[7:0]
crcvalid
Figure 3–3
clk
Message bits
data1
shows a typical application of the CRC Generator and
Preliminary
data2
Generator
data3
CRC
data4
data5
data6
Merge
0
data1
Codeword
data2
© November 2009 Altera Corporation
bits
Chapter 3: Functional Description
data3
checksum
data4
Transmitter
data5
CRC Generator