IPR-CRC Altera, IPR-CRC Datasheet - Page 16

• Manufacturer Part Number: IPR-CRC
• Description: IP CORE Renewal Of IP-CRC
• Manufacturer: Altera

Specifications of IPR-CRC

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

2–6
Simulate the Design
Compile the Design
Program a Device
CRC Compiler User Guide
f
Table 2–1. Generated Files (Sheet 2 of 2)
You can now integrate your custom MegaCore function variation into your design,
simulate, and compile your design.
You can simulate your design using the MegaWizard-generated VHDL or Verilog
HDL IP functional simulation models. These simulation models are generated in the
language you selected in
For an example of simulating a design, refer to the section,
Example” on page
For more information on IP functional simulation models, refer to the
Altera IP in Third-Party Simulation Tools
Handbook.
You can use the Quartus II software to compile your design. Refer to Quartus II Help
for instructions on compiling your design.
After you compile your design, program your targeted Altera device and verify your
design in hardware.
<variation name>.vhd or .v
<variation name>_bb.v
<variation name>.qip
<variation name>_syn.v
testbench/tb.v(hd) or
testbench/tb_multichan.v(hd)
testbench/crcdemo.v(hd) or
testbench/crcdemo_multichan.v(hd)
testbench/crcgen.v(hd) or
testbench/crcgen_multichan.v(hd)
testbench/crcchk.v(hd) or
testbench/crcchk_multichan.v(hd)
File Name
3–8.
“Set Up Simulation” on page
Preliminary
A MegaCore function variation file, which defines a VHDL
or Verilog HDL top-level description of the custom
MegaCore function. Instantiate the entity defined by this
file inside of your design. Include this file when compiling
your design in the Quartus II software.
Verilog HDL black-box file for the MegaCore function
variation. Use this file when using a third-party EDA tool to
synthesize your design.
Contains Quartus II project information for your MegaCore
function variations.
A timing and resource estimation netlist for use in some
third-party synthesis tools. This file is generated when the
option Generate netlist on the EDA page is turned on.
A Verilog or VHDL testbench file that provides a testbench
for the CRC compiler MegaCore function variation.
A Verilog or VHDL example design incorporating a CRC
generator, checker, and other supporting models.
Wrapper for example variations of the CRC Compiler
MegaCore function used in the testbench.
Wrapper for example variations of the CRC Compiler
MegaCore function used in the testbench.
chapter in volume 3 of the Quartus II
2–4.
Description
© November 2009 Altera Corporation
“Running the Testbench
Chapter 2: Getting Started
Simulating
Simulate the Design