IPR-CRC Altera, IPR-CRC Datasheet - Page 20

• Manufacturer Part Number: IPR-CRC
• Description: IP CORE Renewal Of IP-CRC
• Manufacturer: Altera

Specifications of IPR-CRC

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–4
Multi-Channel Operation
CRC Compiler User Guide
Figure 3–6. Checker Operation With Good Codeword
Figure 3–7. Checker Operation With Bad Codeword
For multi-channel (Number of CRC Channels > 1) operations, the CRC Compiler
inserts context memories which allow a generator or checker to process multiple
packets concurrently. Both speed and area optimization variants support multi-
channel operation.
On each datavalid cycle, user applications must set the datachannel input signal
to the channel context in use. The MegaCore function sets the crcchannel output
signal to the same value after a fixed number of clock latency (at the assertion of
crcvalid), to indicate the channel the crcbad or checksum output signal applies
to.
There is no channel switch latency or minimum number of cycles between context
switches, and no restriction on channel ordering is imposed. The latency of a multi-
channel MegaCore function is identical to that of the corresponding single-channel
MegaCore function.
However, there is an fmax penalty in multi-channel operation. After each system reset
(reset_n = 0), there will be a slight delay in terms of the number of clock cycles due
to an internal initialization of the context to a known state. The chaninitdone
output signal is asserted when the internal initialization is done. You must wait until
this output signal is asserted before sending any data to the MegaCore function for
processing.
startofpacket
startofpacket
endofpacket
endofpacket
empty[3:0]
empty[3:0]
datavalid
data[7:0]
datavalid
data[7:0]
crcvalid
crcvalid
crcbad
crcbad
clk
clk
data1
data1
data2
Preliminary
data3
data2
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0
data4
data3
data5
data4
data6
0
data5
checksum
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© November 2009 Altera Corporation
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Chapter 3: Functional Description
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data1
0
Multi-Channel Operation