IPR-CRC Altera, IPR-CRC Datasheet - Page 22

• Manufacturer Part Number: IPR-CRC
• Description: IP CORE Renewal Of IP-CRC
• Manufacturer: Altera

Specifications of IPR-CRC

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–6
Parameters
Table 3–1. MegaWizard Control Settings
CRC Compiler User Guide
CRC Generator
CRC Checker
Number of CRC Channels
Datapath
Symbols per word
Process low-numbered bit in each
symbol first
Process low-numbered symbol first
Register all Avalon-ST inputs
Optimize for: speed
Optimize for: area
CRC Code
Starting value
Number of leading bits to ignore in
First word
Negate checksum
Bit-swap checksum
Register all outputs
Parameter
You specify the parameters for the CRC Compiler MegaCore functions using the
MegaWizard interface.
Creates a generator MegaCore function
Creates a checker MegaCore function
Specifies the number of CRCs supported. All input and output signals are shared
among the channels. Hence, only 1 channel can be processed at any one time.
Selects the width of the data input
Specifies the number of symbols in a datapath, and thus defines the width of each
symbol in bits. A symbol represents the smallest unit of data in a word. For
example, if Datapath is set to 32 bits and Symbols per word is set to 4, the width of
each symbol is 8 bits.
Processes each symbol in reverse order. For example, given the Datapath is 12 bits
and Symbols per word is 3, turning on this parameter causes the MegaCore
function to process “abcd efgh ijkl” as “dcba hgfe lkji”.
Processes the symbols in reverse order. For example, given the Datapath is 12 bits
and Symbols per word is 3, turning on this parameter causes the MegaCore
function to process “abcd efgh ijkl” as “ijkl efgh abcd”.
If both parameters, Process low-numbered bit in each symbol first and Process
low-numbered symbol first are turned on, the MegaCore processes the entire data
in reverse order.
Buffers data, datavalid, startofpacket, endofpacket, and empty
signals with flip-flops
Inserts logic to increase the maximum clock speed
Removes logic to reduce logic utilization and latency
Selects the generator polynomial by name
Presets the CRC register to this value before each packet.
Specifies the number of bits to ignore at the beginning of a packet.
Sets checksum to the one’s complement of the result of the polynomial division.
Not applicable to the CRC checker.
Applies only to CRC Generator. Selecting this parameter reverses the sequence of
the entire output bits. The low-order bits of the remainder are placed in the high-
order bits of the checksum. Select this parameter if data transmission starts from
low-order bit.
Buffers crcvalid and checksum, or crcbad with flip-flops.
Table 3–1
Preliminary
describes each available parameter.
Description
© November 2009 Altera Corporation
Chapter 3: Functional Description
Parameters