IPR-CRC Altera, IPR-CRC Datasheet - Page 23

• Manufacturer Part Number: IPR-CRC
• Description: IP CORE Renewal Of IP-CRC
• Manufacturer: Altera

Specifications of IPR-CRC

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 3: Functional Description
Signals
Signals
Table 3–2. CRC Signals
Testbench
© November 2009 Altera Corporation
clk
reset_n
data[(n-1):0]
datavalid
startofpacket
endofpacket
empty[(n-1):0]
checksum[(n-1):0]
crcbad
crcvalid
Multi-Channel Signals
datachannel[(n-1):0]
chaninitdone
crcchannel[(n-1):0]
Signal
Table 3–2
The testbench shows you a typical variant created by the CRC Compiler. The variant
and the testbench are fixed and may differ from the variant you create.
The testbench is available in both Verilog and VHDL, plaintext except for the CRC IP
Functional Simulation models. The testbench models are synthesizable RTL which
allows you to compile and to run the testbench in hardware. The architecture is
shown in
Direction
Out
Out
Out
Out
Out
In
In
In
In
In
In
In
describes the I/O signals of a CRC MegaCore function.
In
Figure
3–11.
System clock.
Asynchronous reset signal, which is active at 0.
Message bits for generator; codeword bits for checker, where n is a power of 2,
from 1 through 256, (1, 2, 4, 8,16, 32, 64,128, or 256).
Asserted by the source to indicate new packet data.
Asserted by the source to mark the beginning of a packet. This signal is present
only when the parameter Optimize for: speed is set to ON or Number of leading
bits to ignore in First word is greater than 0.
Asserted by the source to mark the end of a packet.
The number of empty symbols during cycles that contain the end of a packet.
This signal must be set to 0 during other cycles when datavalid is
asserted. The value of n equals log
is present only when the parameter Symbols per word is greater than 1.
Computed CRC output, where n equals the order of the generator polynomial.
This signal is present only in CRC generator.
Asserted if the previous packet had an incorrect CRC. This signal is present only
in CRC checker.
Asserted when the core has completed calculation of the checksum or
crcbad value.
The channel on which data is received by the generator or checker. The value of
n equals log
Asserted when the MegaCore function has completed its internal initialization
process and ready to receive data for processing. User applications must wait
for chaninitdone to be asserted before sending data to the MegaCore
function for processing. The MegaCore function reinitializes itself each time the
reset_n signal is asserted.
Indicates the channel whose result is presented at the checksum (generator)
or crcbad (checker) output signal. The value of n equals log
channels).
2
(number of CRC channels).
Preliminary
Description
2
(number of symbols per word). This signal
CRC Compiler User Guide
2
(number of CRC
3–7