IPR-ASI Altera, IPR-ASI Datasheet - Page 31

• Manufacturer Part Number: IPR-ASI
• Description: IP CORE Renewal Of IP-ASI
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-ASI

• Software Application: IP CORE, Interface And Protocols, AUDIO AND VIDEO
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Mfg Application Notes: ASI Demo Video Interface App Note
• Function: Receiver/Transmitter for Digital Video Broadcast
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Appendix A: Constraints
Constraints For ASI Receivers
January 2011 Altera Corporation
Cyclone Devices Only
1
1
Modify the following constraints and apply them to your design. Alternatively, apply
similar constraints to the clocks connected to the rx_serial_clk and rx_clk135
signals on your ASI MegaCore function.
To avoid the u_rx_pll|c0 and u_rx_pll|c2 nodes from getting synthesized away
during analysis and synthesis, make sure the reset port of the core is connected to an
input pin and not to the ground; and apply the following the following additional
constraints on the two nodes:
set_instance_assignment -name IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL ON -to
"u_rx_pll|c0"
set_instance_assignment -name IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL ON -to
"u_rx_pll|c2"
Classic Timing Analyzer
Use the following constraints for the Classic timing analyzer:
set_instance_assignment -name SETUP_RELATIONSHIP "4.43 ns" -from
"u_rx_pll|c0" -to "u_rx_pll|c2"
Where c0 is a 337.5-MHz PLL output and c2 is the 135-MHz PLL output.
set_instance_assignment -name HOLD_RELATIONSHIP "0 ns" -from
"u_rx_pll|c0" -to "u_rx_pll|c2"
TimeQuest Timing Analyzer
Use the following constraints for the TimeQuest timing analyzer:
set_max_delay 4.43 -from {u_rx_pll|altpll:altpll_component|_clk0} -to
{u_rx_pll|altpll:altpll_component|_clk2}
set_min_delay 0 -from {u_rx_pll|altpll:altpll_component|_clk0} -to
{u_rx_pll|altpll:altpll_component|_clk2}
These constraints apply to Cyclone devices only (not Cyclone II, Cyclone III or other
device families).
Classic Timing Analyzer
Use the following constraints for the Classic timing analyzer:
set_instance_assignment -name CLOCK_SETTINGS input_refclk -to rx_refclk
set_global_assignment -name FMAX_REQUIREMENT "27 MHz" -section_id
input_refclk
set_instance_assignment -name CLOCK_SETTINGS rxclk -to
"u_clkdiv|clkdiv"
set_global_assignment -name BASED_ON_CLOCK_SETTINGS input_refclk -
section_id rxclk
set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 5 -section_id
rxclk
set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 25 -section_id
Asynchronous Serial Interface (ASI) MegaCore Function User Guide
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