IPR-ASI Altera, IPR-ASI Datasheet - Page 24

• Manufacturer Part Number: IPR-ASI
• Description: IP CORE Renewal Of IP-ASI
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-ASI

• Software Application: IP CORE, Interface And Protocols, AUDIO AND VIDEO
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Mfg Application Notes: ASI Demo Video Interface App Note
• Function: Receiver/Transmitter for Digital Video Broadcast
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–4
Figure 4–3. Synchronization State Machine
Asynchronous Serial Interface (ASI) MegaCore Function User Guide
8B10B Decoder
Synchronization State Machine
Packet Synchronization
CODE_ERROR
CODE_ERROR
CODE_ERROR
The 8B10B decoder converts 10-bit wide parallel data from 8B10B codes into 8-bit
wide raw data. The decoder detects special characters, code errors (unused codes),
and disparity errors and signals their presence with various flags.
Two consecutive comma characters without any disparity or code error enables word
synchronization. Four consecutive disparity or code errors enables loss of
synchronization and so disable the word synchronization flag. The word
synchronization flag gates the rate matching FIFO write request.
synchronization state machine.
The packet synchronization block looks for the presence of valid TS packets. Valid
packets have either 188 bytes or 204 bytes between synchronization bytes. The
synchronization byte takes the value 0x47.
SYNC_REQ 1
SYNC_REQ 2
IN_SYNC 1
IN_SYNC 2
IN_SYNC 3
IN_SYNC 4
! CODE_ERROR and
KCODE_FOUND
! CODE_ERROR and
KCODE_FOUND
! CODE_ERROR
! CODE_ERROR
! CODE_ERROR
! CODE_ERROR
CODE_ERROR
Chapter 4: Functional Description
January 2011 Altera Corporation
Figure 4–3
shows the
Receiver