IPR-ASI Altera, IPR-ASI Datasheet - Page 13

• Manufacturer Part Number: IPR-ASI
• Description: IP CORE Renewal Of IP-ASI
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-ASI

• Software Application: IP CORE, Interface And Protocols, AUDIO AND VIDEO
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Mfg Application Notes: ASI Demo Video Interface App Note
• Function: Receiver/Transmitter for Digital Video Broadcast
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
MegaWizard Plug-In Manager Flow
MegaWizard Plug-In Manager Flow
January 2011 Altera Corporation
Simulate the System
f
f
1
1
1. Add and parameterize any additional components to the system.
2. Connect the components using the SOPC Builder patch panel.
3. To simulate your SOPC builder system, select Simulate on the System Generation
4. Click Generate to generate the system.
During system generation, SOPC Builder optionally generates a simulation model
and testbench for the entire system, which you can use to easily simulate your system
in any of Altera's supported simulation tools. SOPC Builder also generates a set of
ModelSim Tcl scripts and macros that you can use to compile the testbench, IP
functional simulation models and plain-text RTL design files that describe your
system in the ModelSim simulation software.
For more information about simulating SOPC Builder systems, refer to
the Quartus II Handbook and
Before compiling your design, you must run the Tcl constraint script.
The MegaWizard Plug-In Manager flow allows you to customize the ASI MegaCore
function, and manually integrate the function into your design.
You can alternatively use the IP Advisor to help you start your ASI MegaCore design.
On the Quartus II Tools menu, point to Advisors, and then click IP Advisor. The IP
Advisor guides you through a series of recommendations for selecting,
parameterizing, evaluating, and instantiating an ASI MegaCore function into your
design. It then guides you through a complete Quartus II compilation of your project.
For more information about the MegaWizard Plug-In Manager and the IP Advisor,
refer to the Quartus II Help.
A typical SOPC builder system that enables Ethernet connectivity uses a
scatter/gather DMA controller on each of the transmit and receive paths, and a
Nios II processor for configuration and control.
tab to generate a functional simulation model for the system.
1
Among the files generated by SOPC Builder is the Quartus II IP File (.qip).
This file contains information about a generated IP core or system. In most
cases, the .qip file contains all of the necessary assignments and
information required to process the MegaCore function or system in the
Quartus II compiler. Generally, a single .qip file is generated for each SOPC
Builder system. However, some more complex SOPC Builder components
generate a separate .qip file. In that case, the system .qip file references the
component .qip file.
AN 351: Simulating Nios II
Asynchronous Serial Interface (ASI) MegaCore Function User Guide
Systems.
volume 4
of
2–3