IPR-ASI Altera, IPR-ASI Datasheet - Page 25

• Manufacturer Part Number: IPR-ASI
• Description: IP CORE Renewal Of IP-ASI
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-ASI

• Software Application: IP CORE, Interface And Protocols, AUDIO AND VIDEO
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Mfg Application Notes: ASI Demo Video Interface App Note
• Function: Receiver/Transmitter for Digital Video Broadcast
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Testbench
Testbench
Signals
Table 4–1. Signals (Part 1 of 2)
January 2011 Altera Corporation
asi_rx
cal_blk_clk
gxb_powerdown
reconfig_clk
reconfig_togxb[3:0]
rst
rx_clk135
rx_protocol_in[9:0]
rx_protocol_in_valid
rx_serial_clk
rx_serial_clk90
tx_clk270
tx_clk135
tx_data[7:0]
tx_en
tx_refclk
tx_serdes_in[9:0]
Signal
(1) (2)
(1)
The block first looks for the synchronization byte that indicates the start of the packet,
which is indicated by rx_ts_status[1]. The block then counts valid bytes in the
incoming stream. If a synchronization byte is seen 188 or 204 bytes after the first sync
byte is seen, lock is indicated on rx_ts_[5:4] and end of packet is indicated on
rx_ts_status[2]. If no synchronization byte is seen at either 188 or 204 bytes, the
packet is deemed to have an error and rx_ts_status[3] is asserted. The block then
again starts the search for synchronization bytes.
The testbench instantiates two ASI MegaCore functions—one ASI transmitter, one
ASI receiver.
To test a realistic ASI link, an ASI packet generator creates packets that are sent from
the instantiation of the ASI transmitter to the instantiation of the ASI receiver. A
random serial data delay generator is inserted on the way to mimic random jitter on
the link. The transmitter and receiver are clocked with asynchronous clock sources—
the frequencies differ by 200 ppm, which maximizes the stress that the ASI receiver
sees and is similar to a real link.
Table 4–1
(1) (2)
shows the signals.
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Direction
ASI input.
Calibration clock for Arria GX, Stratix II GX, and Stratix IV
transceiver.
Transceiver block reset and power down. This signal of all the
instances that are to be combined into a single transceiver block
must be connected to a single point; for example, the same input
pin or same logic.
Clock input for the embedded transceiver instance.
Data input for the embedded transceiver instance.
Reset.
135-MHz clock from external PLL.
Protocol input (for split SERDES/protocol).
Valid signal for rx_protocol_in.
337.5-MHz clock from external PLL.
270-MHz clock from external PLL.
135-MHz clock from external PLL (only for hard SERDES).
TS parallel data input into encoder.
Transmit enable. Assert to indicate valid data on tx_data.
27-MHz reference clock for transmitter.
Direct input to transceiver block for split protocol/tranceiver mode.
337.5-MHz clock from external PLL with + 90⋅ phase shift.
Asynchronous Serial Interface (ASI) MegaCore Function User Guide
Description
4–5