IPR-ASI Altera, IPR-ASI Datasheet - Page 17

• Manufacturer Part Number: IPR-ASI
• Description: IP CORE Renewal Of IP-ASI
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-ASI

• Software Application: IP CORE, Interface And Protocols, AUDIO AND VIDEO
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Mfg Application Notes: ASI Demo Video Interface App Note
• Function: Receiver/Transmitter for Digital Video Broadcast
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
Compile the Design and Program a Device
Compile the Design and Program a Device
January 2011 Altera Corporation
4. In the New Test Bench Settings dialog box, perform the following steps:
5. On the Processing menu, point to Start and click Start Analysis & Elaboration.
6. On the Tools menu, point to Run EDA Simulation Tool and click EDA RTL
You can use the Quartus II software to compile your design. Refer to Quartus II Help
for instructions on performing compilation.
After you have compiled your design, program your targeted Altera device and
verify your design in hardware.
a. In the Test bench name box, type the testbench setup name.
b. In the Top level module in test bench box, type the following as the project
c. In the Design instance in test bench box, type the name of the top-level
d. Under Simulation period, set End simulation at to 500 µs.
e. Add the testbench files. In the File name field, browse to the location of the
f. Select the files and click OK.
Simulation.
testbench name, tb_asi_mc.
instance.
testbench, tb_asi_mc, click Open and then click Add.
Asynchronous Serial Interface (ASI) MegaCore Function User Guide
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