IPR-ASI Altera, IPR-ASI Datasheet - Page 26

• Manufacturer Part Number: IPR-ASI
• Description: IP CORE Renewal Of IP-ASI
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-ASI

• Software Application: IP CORE, Interface And Protocols, AUDIO AND VIDEO
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Mfg Application Notes: ASI Demo Video Interface App Note
• Function: Receiver/Transmitter for Digital Video Broadcast
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–6
Table 4–1. Signals (Part 2 of 2)
Asynchronous Serial Interface (ASI) MegaCore Function User Guide
asi_tx
reconfig_fromgxb[16:0]
rx_data[7:0]
rx_data_clk
rx_serdes_out[9:0]
rx_serdes_out_valid
rx_ts_status[7:0]
tx_protocol_out[9:0]
Note for
(1) This signal is available for Stratix IV transceivers only.
(2) In Quartus II version 8.1 and higher, the Stratix IV transceivers need RX buffer calibration through an altgx_reconfig (DPRIO) controller. You
must connect the ports to the altgx_reconfig controller externally. For further information on the RX buffer calibration, refer to Stratix IV
DPRIO documentation. If you are using Quartus II software version 10.1, upgrade the ASI MegaCore function to version 10.1 as well.
Table
4–1:
Signal
(1) (2)
Output
Output
Output
Output
Output
Output
Output
Output
Direction
ASI output.
Data output from the embedded transceiver instance.
Decoded parallel TS data out of receiver.
135-MHz parallel clock, which you can use to clock
rx_data[7:0].
Raw data from transceiver block before decoding.
Valid signal out of the transceiver.
TS status bits.
0 indicates receiver data valid
1 indicates start of packet
2 indicates end of packet
3 indicates receiver error
5:4 indicates 00 is unlocked; 01 is 204 byte packet lock, 11 is 188
byte packet lock
6 indicates TS serial polarity
7 indicates that the data on rx_data[7:0] is a valid word from the
8B10B decoder. Unlike rx_ts_status[0], this signal is not
dependent on the correct packet or synchronization structure of the
stream.
Output from transmitter protocol block for split
protocol/transceiver mode.
Description
Chapter 4: Functional Description
January 2011 Altera Corporation
Signals