IPR-ASI Altera, IPR-ASI Datasheet - Page 28

• Manufacturer Part Number: IPR-ASI
• Description: IP CORE Renewal Of IP-ASI
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-ASI

• Software Application: IP CORE, Interface And Protocols, AUDIO AND VIDEO
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Mfg Application Notes: ASI Demo Video Interface App Note
• Function: Receiver/Transmitter for Digital Video Broadcast
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

A–2
Asynchronous Serial Interface (ASI) MegaCore Function User Guide
Specify Clock Characteristics
Use the following constraints for the TimeQuest timing analyzer:
■
create_clock -name {rx_clk135} -period 7.407 -waveform { 0.000 3.703 }
[get_ports {rx_clk135}]
■
create_clock -name {tx_clk135} -period 7.407 -waveform { 0.000 3.703 }
[get_ports {tx_clk135}]
create_clock -name {tx_refclk} -period 37.037 -waveform { 0.000 18.518 }
[get_ports {tx_refclk}]
■
create_clock -name {rx_clk135} -period 7.407 -waveform { 0.000 3.703 }
[get_ports {rx_clk135}]
create_clock -name {rx_serial_clk} -period 2.963 -waveform { 0.000 1.481
} [get_ports {rx_serial_clk}]
create_clock -name {rx_serial_clk90} -period 2.963 -waveform { 0.000
1.481 } [get_ports {rx_serial_clk90}]
■
create_clock -name {tx_clk270} -period 3.704 -waveform { 0.000 1.852 }
[get_ports {tx_clk270}]
create_clock -name {tx_refclk} -period 37.037 -waveform { 0.000 18.518
} [get_ports {tx_refclk}]
Define the Setup and Hold Relationship between the 135-MHz Clocks and the
337.5-MHz zero-degree Clocks
These constraints apply only to Soft Transceiver ASI.
■
■
Use the set_min_delay command to specify an absolute minimum delay for a given
path.
■
set_min_delay -from
{rx_clk135}] 0.000
■
set_min_delay -from
{tx_clk270}] 0.000
Use the set_max_delay command to specify an absolute maximum delay for a given
path.
■
set_max_delay -from
{rx_clk135}] 4.430
■
set_max_delay -from
{tx_clk270}] 33.333
ASI RX (Hard Transceiver) (rx_clk135 = 135 MHz)
ASI TX (Hard Transceiver) (tx_clk135 = 135 MHz, tx_refclk = 27 MHz)
ASI RX (Soft Transceiver) (rx_clk135 = 135 MHz, rx_serial_clk = 337.5 MHz,
rx_serial_clk90 = 337.5 MHz)
ASI TX (Soft Transceiver) (tx_clk270 = 270 MHz, tx_refclk = 27 MHz)
Setup - 1.5 clocks (4.43 ns) from the 337.5-MHz zero-degree clock to the 135-MHz
clock
Hold - zero clocks from the 337.5-MHz clock to the 135-MHz clock
ASI RX (Soft Transceiver)
ASI TX (Soft Transceiver)
ASI RX (Soft Transceiver)
ASI TX (Soft Transceiver)
[get_clocks {rx_serial_clk}]
[get_clocks {tx_refclk}]
[get_clocks {rx_serial_clk}]
[get_clocks {tx_refclk}]
Constrain Design With TimeQuest Timing Analyzer
-to
-to
January 2011 Altera Corporation
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-to
[get_clocks
[get_clocks
Appendix A: Constraints
[get_clocks
[get_clocks