IPR-ASI Altera, IPR-ASI Datasheet - Page 19

• Manufacturer Part Number: IPR-ASI
• Description: IP CORE Renewal Of IP-ASI
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-ASI

• Software Application: IP CORE, Interface And Protocols, AUDIO AND VIDEO
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Mfg Application Notes: ASI Demo Video Interface App Note
• Function: Receiver/Transmitter for Digital Video Broadcast
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Table 3–1. Parameters
January 2011 Altera Corporation
Currently selected device
family
Interface type
Transceiver and protocol
Use soft logic for
transceiver
Parameter
1
Table 3–1
You can change the page that the MegaWizard Plug-In Manager displays by clicking
Next or Back at the bottom of the dialog box. You can move directly to a named page
by clicking the Parameter Settings, EDA, or Summary tab.
—
Receiver or transmitter
Generate transceiver and protocol
blocks, or generate transceiver only,
or generate protocol blocks only
On or off
summarizes the parameters.
Range
Asynchronous Serial Interface (ASI) MegaCore Function User Guide
Shows the device family that you chose in your
Quartus II project.
Select a receiver or transmitter for you custom
variation.
Select the blocks for your custom variation.
For Stratix II GX, Stratix IV GX and Stratix GX
devices, specify soft logic for the transceiver. When
you turn on Use soft logic for transceiver, the
transceiver is implemented in the device’s logic,
otherwise the design uses a Stratix II GX, Stratix IV
GX or Stratix GX transceiver.
3. Parameter Settings
Description