IPR-ASI Altera, IPR-ASI Datasheet - Page 15

• Manufacturer Part Number: IPR-ASI
• Description: IP CORE Renewal Of IP-ASI
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-ASI

• Software Application: IP CORE, Interface And Protocols, AUDIO AND VIDEO
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Mfg Application Notes: ASI Demo Video Interface App Note
• Function: Receiver/Transmitter for Digital Video Broadcast
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
MegaWizard Plug-In Manager Flow
Table 2–2. Generated Files
January 2011 Altera Corporation
<variation name>.v or .vhd
<variation name>.cmp
<variation name>.bsf
<variation name>.html
<variation name>.ppf
<variation name>.vo or .vho
<variation name>_bb.v
<variation name>.qip
Simulate the Design
f
File Name
Table 2–2
directory. The names and types of files specified in the summary vary based on
whether you created your design with VHDL or Verilog HDL.
You can now integrate your custom MegaCore function variation into your design
and simulate and compile.
This section describes the following simulation techniques:
■
■
■
Simulate with IP Functional Simulation Models
You can simulate your design using the MegaWizard-generated VHDL and Verilog
HDL IP functional simulation models.
You can use the IP functional simulation model with any Altera-supported VHDL or
Verilog HDL simulator. To use the IP functional simulation model, create a suitable
testbench.
For more information on IP functional simulation models, refer to the
Altera IP in Third-Party Simulation Tools
Simulate with IP Functional Simulation Models
Simulate with the ModelSim Simulator
Simulating in Third-Party Simulation Tools Using NativeLink
describes the generated files and other files that may be in your project
A MegaCore function variation file, which defines a VHDL or Verilog HDL
description of the custom MegaCore function. Instantiate the entity defined by
this file inside of your design. Include this file when compiling your design in
the Quartus II software.
A VHDL component declaration file for the MegaCore function variation. Add
the contents of this file to any VHDL architecture that instantiates the
MegaCore function.
Quartus II symbol file for the MegaCore function variation. You can use this file
in the Quartus II block diagram editor.
MegaCore function report file.
This XML file describes the MegaCore pin attributes to the Quartus II Pin
Planner. MegaCore pin attributes include pin direction, location, I/O standard
assignments, and drive strength. If you launch IP Toolbench outside of the Pin
Planner application, you must explicitly load this file to use Pin Planner.
VHDL or Verilog HDL IP functional simulation model.
A Verilog HDL black-box file for the MegaCore function variation. Use this file
when using a third-party EDA tool to synthesize your design.
Contains Quartus II project information for your MegaCore function variations.
Asynchronous Serial Interface (ASI) MegaCore Function User Guide
chapter in volume 3 of the Quartus II Handbook.
Description
Simulating
2–5