NAND01GW3B2BN6E NUMONYX, NAND01GW3B2BN6E Datasheet - Page 26

• Manufacturer Part Number: NAND01GW3B2BN6E
• Description: IC, FLASH, 1GB, 25µS, TSOP-48
• Manufacturer: NUMONYX

Specifications of NAND01GW3B2BN6E

• Memory Type: Flash
• Memory Size: 1GB
• Access Time: 25µs
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: TSOP
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +85°C
• Voltage, Vcc: 3.3V
• Rohs Compliant: Yes
• Interface: Serial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device operations
6.4
26/60
Copy back program
The copy back program operation is used to copy the data stored in one page and
reprogram it in another page.
The copy back program operation does not require external memory and so the operation is
faster and more efficient because the reading and loading cycles are not required. The
operation is particularly useful when a portion of a block is updated and the rest of the block
needs to be copied to the newly assigned block.
If the copy back program operation fails an error is signalled in the status register. However
as the standard external ECC cannot be used with the copy back program operation bit error
due to charge loss cannot be detected. For this reason it is recommended to limit the
number of copy back program operations on the same data and or to improve the
performance of the ECC.
The copy back program operation requires four steps:
1.
2.
3.
To see the data input cycle for modifying the source page and an example of the copy back
program operation refer to
A data input cycle to modify a portion or a multiple distant portion of the source page, is
shown in
Table 11.
Table 12.
1 Gbit
2 Gbits
1 Gbit
2 Gbits
The first step reads the source page. The operation copies all 1056 words/ 2112 bytes
from the page into the data buffer. It requires:
–
–
–
When the device returns to the ready state (Ready/Busy High), the next bus write cycle
of the command is given with the 4 or 5 bus cycles to input the target page address
(see
for the source and target pages
Then the confirm command is issued to start the P/E/R controller.
Figure
one bus write cycle to setup the command
4 or 5 bus write cycles to input the source page address (see
one bus write cycle to issue the confirm command code
Table 6
Density
Density
Copy back program x8 addresses
Copy back program x16 addresses
12.
and
Table
Figure
7). Refer to
11.
Table 11
Same address for source and target pages
Same address for source and target pages
for the addresses that must be the same
no constraint
no constraint
NAND01G-B2B, NAND02G-B2C
A28
A27
Table 6
and
Table
7)