STM32W108B-SK STMicroelectronics, STM32W108B-SK Datasheet - Page 48
STM32W108B-SK
Manufacturer Part Number
STM32W108B-SK
Description
STARTER KIT FOR STM32W108
Manufacturer
STMicroelectronics
Series
STM32r
Type
MCUr
Datasheets
1.STM32W108B-KEXT.pdf
(3 pages)
2.STM32W108B-KEXT.pdf
(209 pages)
3.STM32W108B-KEXT.pdf
(27 pages)
4.STM32W108B-KEXT.pdf
(6 pages)
5.STM32W108B-SK.pdf
(21 pages)
6.STM32W108B-KEXT.pdf
(14 pages)
7.STM32W108B-KEXT.pdf
(36 pages)
Specifications of STM32W108B-SK
Featured Product
STM32 Cortex-M3 Companion Products
Contents
Board
Silicon Manufacturer
ST Micro
Core Architecture
ARM
Core Sub-architecture
Cortex - M3
Silicon Core Number
STM32
Silicon Family Name
STM32W108xx
Kit Contents
Board
Features
IEEE
Mfg Application Notes
STM32W108 Adjacent Channel Rejection Measurements
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- STM32W108B-KEXT PDF datasheet
- STM32W108B-KEXT PDF datasheet #2
- STM32W108B-KEXT PDF datasheet #3
- STM32W108B-KEXT PDF datasheet #4
- STM32W108B-SK PDF datasheet #5
- STM32W108B-KEXT PDF datasheet #6
- STM32W108B-KEXT PDF datasheet #7
- Current page: 48 of 209
- Download datasheet (3Mb)
System modules
48/209
31
15
31
15
30
14
30
14
Sleep timer interrupt mask register (INT_SLEEPTMRCFG)
Address:
Reset value:
Sleep timer clock source enables (SLEEPTMR_CLKEN)
This timer controls the low power clock gated modes.
Clearing CLKRC_EN before executing WFE with SLEEPDEEP bit set in the NVIC System
control register causes DEEP_SLEEP2 to be entered. Setting this bit causes
DEEP_SLEEP1 to be entered.
Address:
Reset value:
Bit 2 INT_ SLEEPTMR CMPB: Sleep timer compare B
Bit 1 INT_SLEEPTMRCMPA: Sleep timer compare A
Bit 0 INT_SLEEPTMRWRAP: Sleep timer overflow
Bit 1 SLEEPTMR_CLK10KEN: Enables 10kHz internal RC during deep
Bit 0 SLEEPTMR_CLK32KEN: Enables 32kHz external XTAL
29
13
29
13
Note: Bits are cleared when set to ‘1’.
Note: Bits are cleared when set to ‘1’.
28
12
28
12
27
11
27
11
0x4000 A054
0x0000 0000
0x4000 0008
0x0000 0002
26
10
26
10
25
Reserved
9
Reserved
25
9
r
Doc ID 16252 Rev 8
r
24
8
24
8
Reserved
Reserved
23
7
23
7
22
6
22
6
21
5
21
5
STM32W108CB, STM32W108HB
20
4
20
4
19
3
19
3
18
2
SLEEP
CMPB
INT_
TMR
18
rw
2
CLK10K
SLEEP
TMR_
EN
17
rw
1
SLEEP
CMPA
INT_
TMR
17
rw
1
CLK32K
SLEEP
TMR_
SLEEP
WRAP
EN
16
rw
INT_
TMR
0
16
rw
0
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