STM32W108B-SK STMicroelectronics, STM32W108B-SK Datasheet - Page 191
STM32W108B-SK
Manufacturer Part Number
STM32W108B-SK
Description
STARTER KIT FOR STM32W108
Manufacturer
STMicroelectronics
Series
STM32r
Type
MCUr
Datasheets
1.STM32W108B-KEXT.pdf
(3 pages)
2.STM32W108B-KEXT.pdf
(209 pages)
3.STM32W108B-KEXT.pdf
(27 pages)
4.STM32W108B-KEXT.pdf
(6 pages)
5.STM32W108B-SK.pdf
(21 pages)
6.STM32W108B-KEXT.pdf
(14 pages)
7.STM32W108B-KEXT.pdf
(36 pages)
Specifications of STM32W108B-SK
Featured Product
STM32 Cortex-M3 Companion Products
Contents
Board
Silicon Manufacturer
ST Micro
Core Architecture
ARM
Core Sub-architecture
Cortex - M3
Silicon Core Number
STM32
Silicon Family Name
STM32W108xx
Kit Contents
Board
Features
IEEE
Mfg Application Notes
STM32W108 Adjacent Channel Rejection Measurements
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- STM32W108B-KEXT PDF datasheet
- STM32W108B-KEXT PDF datasheet #2
- STM32W108B-KEXT PDF datasheet #3
- STM32W108B-KEXT PDF datasheet #4
- STM32W108B-SK PDF datasheet #5
- STM32W108B-KEXT PDF datasheet #6
- STM32W108B-KEXT PDF datasheet #7
- Current page: 191 of 209
- Download datasheet (3Mb)
STM32W108CB, STM32W108HB
Note:
Table 47
Table
Table 47.
The signal-ended ADC measurements are limited in their range and only guaranteed for
accuracy within the limits shown in this table. The ADC's internal design allows for
measurements outside of this range (±200 mV) when the input buffer is disabled, but the
accuracy of such measurements is not guaranteed. The maximum input voltage is of more
interest to the differential sampling where a differential measurement might be small, but a
common mode can push the actual input voltage on one of the signals towards the upper
voltage limit.
VREF
VREF output current
VREF load capacitance
External VREF voltage range
External VREF input impedance
Minimum input voltage
Maximum input voltage
Single-ended signal range
Differential signal range
Common mode range
Input referred ADC offset
Input Impedance
Input buffer disabled
Input buffer enabled
Input buffer disabled
Input buffer enabled
Input buffer disabled
Input buffer enabled
Input buffer disabled
Input buffer enabled
Input buffer disabled
Input buffer enabled
1 MHz sample clock
6 MHz sample clock
Not sampling
46.
lists other specifications for the ADC not covered in
Parameter
ADC characteristics
Doc ID 16252 Rev 8
-VDD_PADS + 0.1
-VREF
Min.
1.17
1.1
0.1
0.1
-10
0.5
10
–
–
1
0
–
–
0
0
1
VDD_PADS/2
Typ.
1.2
1.2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Table
Electrical characteristics
44,
+VDD_PADS - 0.1
VDD_PADS – 0.1
VDD_PADS - 0.1
Table
+VREF
VREF
VREF
VREF
Max.
1.23
1.3
10
10
1
–
–
–
–
–
–
45, and
191/209
Units
mV
mA
MΩ
MΩ
nF
V
V
V
V
V
V
V
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