STM32W108B-SK STMicroelectronics, STM32W108B-SK Datasheet - Page 145
STM32W108B-SK
Manufacturer Part Number
STM32W108B-SK
Description
STARTER KIT FOR STM32W108
Manufacturer
STMicroelectronics
Series
STM32r
Type
MCUr
Datasheets
1.STM32W108B-KEXT.pdf
(3 pages)
2.STM32W108B-KEXT.pdf
(209 pages)
3.STM32W108B-KEXT.pdf
(27 pages)
4.STM32W108B-KEXT.pdf
(6 pages)
5.STM32W108B-SK.pdf
(21 pages)
6.STM32W108B-KEXT.pdf
(14 pages)
7.STM32W108B-KEXT.pdf
(36 pages)
Specifications of STM32W108B-SK
Featured Product
STM32 Cortex-M3 Companion Products
Contents
Board
Silicon Manufacturer
ST Micro
Core Architecture
ARM
Core Sub-architecture
Cortex - M3
Silicon Core Number
STM32
Silicon Family Name
STM32W108xx
Kit Contents
Board
Features
IEEE
Mfg Application Notes
STM32W108 Adjacent Channel Rejection Measurements
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- STM32W108B-KEXT PDF datasheet
- STM32W108B-KEXT PDF datasheet #2
- STM32W108B-KEXT PDF datasheet #3
- STM32W108B-KEXT PDF datasheet #4
- STM32W108B-SK PDF datasheet #5
- STM32W108B-KEXT PDF datasheet #6
- STM32W108B-KEXT PDF datasheet #7
- Current page: 145 of 209
- Download datasheet (3Mb)
STM32W108CB, STM32W108HB
10.3.5
31
15
rw
Bits [14:12] TIM_OC2M: Output Compare 2 Mode. (Applies only if TIM_CC2S = 0
30
14
rw
TIM_IC2F
TIM_OC2M
Bit 11 TIM_OC2BE: Output Compare 2 Buffer Enable. (Applies only if TIM_CC2S = 0
Timer x capture/compare mode register 1 (TIMx_CCMR1)
Address offset: 0xE018 (TIM1) and 0xF018 (TIM2)
Reset value:
Timer channels can be programmed as inputs (capture mode) or outputs (compare mode).
The direction of channel y is defined by TIM_CCyS in this register.
The other bits in this register have different functions in input and in output modes. The
TIM_OC* fields only apply to a channel configured as an output (TIM_CCyS = 0), and the
TIM_IC* fields only apply to a channel configured as an input (TIM_CCyS > 0).
29
13
rw
Define the behavior of the output reference signal OC2REF from which OC2 derives. OC2REF
is active high whereas OC2''s active level depends on the TIM_CC2P bit.
000: Frozen - The comparison between the output compare register TIMx_CCR2 and the
counter TIMx_CNT has no effect on the outputs.
001: Set OC2REF to active on match. The OC2REF signal is forced high when the counter
TIMx_CNT matches the capture/compare register 2 (TIMx_CCR2)
010: Set OC2REF to inactive on match. OC2REF signal is forced low when the counter
TIMx_CNT matches the capture/compare register 2 (TIMx_CCR2).
011: Toggle - OC2REF toggles when TIMx_CNT = TIMx_CCR2.
100: Force OC2REF inactive.
101: Force OC2REF active.
110: PWM mode 1 - In up-counting, OC2REF is active as long as TIMx_CNT < TIMx_CCR2,
otherwise OC2REF is inactive. In down-counting, OC2REF is inactive if
TIMx_CNT > TIMx_CCR2, otherwise OC2REF is active.
111: PWM mode 2 - In up-counting, OC2REF is inactive if TIMx_CNT < TIMx_CCR2, otherwise
OC2REF is active. In down-counting, OC2REF is active if TIMx_CNT > TIMx_CCR2, otherwise
it is inactive.
Note: In PWM mode 1 or 2, the OC2REF level changes only when the result of the
0: Buffer register for TIMx_CCR2 is disabled. TIMx_CCR2 can be written at anytime, the new
value is used by the shadow register immediately.
1: Buffer register for TIMx_CCR2 is enabled. Read/write operations access the buffer register.
TIMx_CCR2 buffer value is loaded in the shadow register at each update event.
Note: The PWM mode can be used without enabling the buffer register only in one pulse mode
28
12
rw
comparison changes or when the output compare mode switches from “frozen” mode to
“PWM” mode.
(TIM_OPM bit set in the TIMx_CR2 register), otherwise the behavior is undefined.
TIM_O
C2BE
TIM_IC2PSC
27
11
rw
0x0000 0000
TIM_O
C2FE
26
10
rw
25
TIM_CC2S
9
Doc ID 16252 Rev 8
rw
24
8
Reserved
23
rw
7
22
rw
6
TIM_IC1F
TIM_OC1M
21
rw
5
20
rw
4
General-purpose timers
TIM_O
C1BE
TIM_IC1PSC
19
rw
3
TIM_O
C1FE
18
rw
2
17
TIM_CC1S
1
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