STM32W108B-SK STMicroelectronics, STM32W108B-SK Datasheet - Page 135
STM32W108B-SK
Manufacturer Part Number
STM32W108B-SK
Description
STARTER KIT FOR STM32W108
Manufacturer
STMicroelectronics
Series
STM32r
Type
MCUr
Datasheets
1.STM32W108B-KEXT.pdf
(3 pages)
2.STM32W108B-KEXT.pdf
(209 pages)
3.STM32W108B-KEXT.pdf
(27 pages)
4.STM32W108B-KEXT.pdf
(6 pages)
5.STM32W108B-SK.pdf
(21 pages)
6.STM32W108B-KEXT.pdf
(14 pages)
7.STM32W108B-KEXT.pdf
(36 pages)
Specifications of STM32W108B-SK
Featured Product
STM32 Cortex-M3 Companion Products
Contents
Board
Silicon Manufacturer
ST Micro
Core Architecture
ARM
Core Sub-architecture
Cortex - M3
Silicon Core Number
STM32
Silicon Family Name
STM32W108xx
Kit Contents
Board
Features
IEEE
Mfg Application Notes
STM32W108 Adjacent Channel Rejection Measurements
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- STM32W108B-KEXT PDF datasheet
- STM32W108B-KEXT PDF datasheet #2
- STM32W108B-KEXT PDF datasheet #3
- STM32W108B-KEXT PDF datasheet #4
- STM32W108B-SK PDF datasheet #5
- STM32W108B-KEXT PDF datasheet #6
- STM32W108B-KEXT PDF datasheet #7
- Current page: 135 of 209
- Download datasheet (3Mb)
STM32W108CB, STM32W108HB
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Figure 46. Gating Timer 2 with enable of Timer 1
Using one timer to start the other timer
In this example, the enable of Timer 2 is set with the update event of Timer 1. Refer to
Figure 44
zero) on the divided internal clock as soon as Timer 1 generates the update event.
When Timer 2 receives the trigger signal its TIM_CEN bit is automatically set and the
counter counts until 0 is written to the TIM_CEN bit in the TIM2_CR1 register. Both counter
clock frequencies are divided by 3 by the prescaler compared to CK_INT (fCK_CNT =
fCK_INT/3).
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Reset Timer 2 by writing 1 in the TIM_UG bit (TIM2_EGR register).
Initialize Timer 2 to 0xE7 by writing 0xE7 in the Timer 2 counter (TIM2_CNTL).
Enable Timer 2 by writing 1 in the TIM_CEN bit (TIM2_CR1 register).
Start Timer 1 by writing 1 in the TIM_CEN bit (TIM1_CR1 register).
Stop Timer 1 by writing 0 in the TIM_CEN bit (TIM1_CR1 register).
Configure Timer 1 in master mode to send its update event as trigger output
(TIM_MMS = 010 in the TIM1_CR2 register).
Configure the Timer 1 period (TIM1_ARR register).
Configure Timer 2 to get the input trigger from Timer 1 (TIM_TS = 000 in the
TIM2_SMCR register).
Configure Timer 2 in trigger mode (TIM_SMS = 110 in the TIM2_SMCR register).
Start Timer 1: Write 1 in the TIM_CEN bit (TIM1_CR1 register).
for connections. Timer 2 starts counting from its current value (which can be non-
Doc ID 16252 Rev 8
General-purpose timers
135/209
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