STM32W108B-SK STMicroelectronics, STM32W108B-SK Datasheet - Page 138

• Manufacturer Part Number: STM32W108B-SK
• Description: STARTER KIT FOR STM32W108
• Manufacturer: STMicroelectronics
• Series: STM32r
• Type: MCUr

Specifications of STM32W108B-SK

• Featured Product: STM32 Cortex-M3 Companion Products
• Contents: Board
• Silicon Manufacturer: ST Micro
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: STM32
• Silicon Family Name: STM32W108xx
• Kit Contents: Board
• Features: IEEE
• Mfg Application Notes: STM32W108 Adjacent Channel Rejection Measurements
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

General-purpose timers
10.2
138/209
Table 26.
Interrupts
Each timer has its own ARM® Cortex-M3 vectored interrupt with programmable priority.
Writing 1 to the INT_TIMx bit in the INT_CFGSET register enables the TIMx interrupt, and
writing 1 to the INT_TIMx bit in the INT_CFGCLR register disables it.
on page 170
Several kinds of timer events can generate a timer interrupt, and each has a status flag in
the INT_TIMxFLAG register to identify the reason(s) for the interrupt:
●
●
●
Clear bits in INT_TIMxFLAG by writing a 1 to their bit position. When a channel is in capture
mode, reading the TIMx_CCRy register will also clear the INT_TIMCCRyIF bit.
The INT_TIMxCFG register controls whether or not the INT_TIMxFLAG bits actually request
an ARM® Cortex-M3 timer interrupt. Only the events whose bits are set to 1 in
INT_TIMxCFG can do so.
If an input capture or output compare event occurs and its INT_TIMMISSCCyIF is already
set, the corresponding capture/compare missed flag is set in the INT_TMRxMISS register.
Clear a bit in the INT_TMRxMISS register by writing a 1 to it.
TIMxMSK
TIMxCLK
OCyREF
INT_TIMTIF - set by a rising edge on an external trigger, either edge in gated mode
INT_TIMCCRyIF -set by a channel y input capture or output compare event
INT_TIMUIF - set by an update event
TIMxCy
TIyFPy
Signal
ICyPS
PCLK
TRGI
ITR0
OCy
TIy
Timer signal descriptions (continued)
describes the interrupt system in detail.
Internal/external
External
External
External
External
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Doc ID 16252 Rev 8
Input capture signal after filtering, edge detection and
prescaling: input to the capture register.
Internal trigger input: connected to the other timer's output,
TRGO.
Output compare: TIMxCy when used as an output. Same as
OCyREF but includes possible polarity inversion.
Output compare reference: always active high, but may be
inverted to produce OCy.
Peripheral clock connects to CK_INT and used to clock input
filtering. Its frequency is 12MHz if using the 24MHz crystal
oscillator and 6Mhz if using the 12MHz RC oscillator.
Timer input: TIMxCy when used as a timer input.
Timer input after filtering and polarity selection.
Timer channel at a GPIO pin: can be a capture input (ICy) or
a compare output (OCy).
Clock input (if selected) to the external trigger signal (ETR).
Clock mask (if enabled) AND'ed with the other timer's
TIMxCLK signal.
Trigger input for slave mode controller.
STM32W108CB, STM32W108HB
Description
Section 12: Interrupts