STM32W108B-SK STMicroelectronics, STM32W108B-SK Datasheet - Page 141

• Manufacturer Part Number: STM32W108B-SK
• Description: STARTER KIT FOR STM32W108
• Manufacturer: STMicroelectronics
• Series: STM32r
• Type: MCUr

Specifications of STM32W108B-SK

• Featured Product: STM32 Cortex-M3 Companion Products
• Contents: Board
• Silicon Manufacturer: ST Micro
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: STM32
• Silicon Family Name: STM32W108xx
• Kit Contents: Board
• Features: IEEE
• Mfg Application Notes: STM32W108 Adjacent Channel Rejection Measurements
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

STM32W108CB, STM32W108HB
10.3.3
TIM_E
TP
31
15
rw
TIM_E
CE
30
14
rw
Bits [6:4] TIM_MMS: Master Mode Selection
Timer x slave mode control register (TIMx_SMCR)
Address offset: 0xE008 (TIM1) and 0xF008 (TIM2)
Reset value:
Bit 15 TIM_ETP: External Trigger Polarity
29
13
TIM_ETPS
rw
This selects the information to be sent in master mode to a slave timer for synchronization
using the trigger output (TRGO).
000: Reset - the TIM_UG bit in the TMRx_EGR register is trigger output.
If the reset is generated by the trigger input (slave mode controller configured in reset mode),
then the signal on TRGO is delayed compared to the actual reset.
001: Enable - counter enable signal CNT_EN is trigger output.
This mode is used to start both timers at the same time or to control a window in which a slave
timer is enabled. The counter enable signal is generated by either the TIM_CEN control bit or
the trigger input when configured in gated mode. When the counter enable signal is controlled
by the trigger input there is a delay on TRGO except if the master/slave mode is selected (see
the TIM_MSM bit description in TMRx_SMCR register).
010: Update - update event is trigger output.
This mode allows a master timer to be a prescaler for a slave timer.
011: Compare Pulse.
The trigger output sends a positive pulse when the TIM_CC1IF flag is to be set (even if it was
already high) as soon as a capture or a compare match occurs.
100: Compare - OC1REF signal is trigger output.
101: Compare - OC2REF signal is trigger output.
110: Compare - OC3REF signal is trigger output.
111: Compare - OC4REF signal is trigger output.
This bit selects whether ETR or the inverse of ETR is used for trigger operations.
0: ETR is non-inverted, active at a high level or rising edge.
1: ETR is inverted, active at a low level or falling edge.
28
12
27
11
0x0000 0000
26
10
TIM_ETF
rw
25
9
Doc ID 16252 Rev 8
24
8
Reserved
TIM_M
SM
23
rw
7
22
6
TIM_TS
rw
21
5
20
4
General-purpose timers
Reserv
19
ed
3
18
2
TIM_SMS
17
rw
1
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16
0