STM32W108B-SK STMicroelectronics, STM32W108B-SK Datasheet - Page 152

• Manufacturer Part Number: STM32W108B-SK
• Description: STARTER KIT FOR STM32W108
• Manufacturer: STMicroelectronics
• Series: STM32r
• Type: MCUr

Specifications of STM32W108B-SK

• Featured Product: STM32 Cortex-M3 Companion Products
• Contents: Board
• Silicon Manufacturer: ST Micro
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: STM32
• Silicon Family Name: STM32W108xx
• Kit Contents: Board
• Features: IEEE
• Mfg Application Notes: STM32W108 Adjacent Channel Rejection Measurements
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

General-purpose timers
10.3.10
10.3.11
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31
15
31
15
30
14
30
14
Bits [15:0] TIM_ARR: Auto-reload value
Bits [15:0] TIM_CCR: Capture/compare value
Timer x auto-reload register (TIMx_ARR)
Address offset: 0xE02C (TIM1) and 0xF02C (TIM2)
Reset value:
Timer x capture/compare 1 register (TIMx_CCR1)
Address offset: 0xE034 (TIM1) and 0xF034 (TIM2)
Reset value:
29
13
29
13
TIM_ARR is the value to be loaded in the shadow auto-reload register.
The auto-reload register is buffered. Writing or reading the auto-reload register accesses the
buffer register. The content of the buffer register is transfered in the shadow register
permanently or at each update event UEV, depending on the auto-reload buffer enable bit
(TIM_ARBE) in TMRx_CR1 register. The update event is sent when the counter reaches the
overflow point (or underflow point when down-counting) and if the TIM_UDIS bit equals 0 in the
TMRx_CR1 register. It can also be generated by software. The counter is blocked while the
auto-reload value is 0.
If the CC1 channel is configured as an output (TIM_CC1S = 0):
TIM_CCR1 is the buffer value to be loaded in the actual capture/compare 1 register. It is loaded
permanently if the preload feature is not selected in the TMR1_CCMR1 register (bit OC1PE).
Otherwise the buffer value is copied to the shadow capture/compare 1 register when an update
event occurs. The active capture/compare register contains the value to be compared to the
counter TMR1_CNT and signaled on the OC1 output.
If the CC1 channel is configured as an input (TIM_CC1S is not 0):
CCR1 is the counter value transferred by the last input capture 1 event (IC1).
28
12
28
12
27
11
27
11
0x0000 0000
0x0000 0000
26
10
26
10
25
25
9
9
Doc ID 16252 Rev 8
24
24
8
8
TIM_CCR
Reserved
TIM_ARR
Reserved
rw
rw
23
23
7
7
22
22
6
6
21
21
5
5
STM32W108CB, STM32W108HB
20
20
4
4
19
19
3
3
18
18
2
2
17
17
1
1
16
16
0
0