STM32W108B-SK STMicroelectronics, STM32W108B-SK Datasheet - Page 189
STM32W108B-SK
Manufacturer Part Number
STM32W108B-SK
Description
STARTER KIT FOR STM32W108
Manufacturer
STMicroelectronics
Series
STM32r
Type
MCUr
Datasheets
1.STM32W108B-KEXT.pdf
(3 pages)
2.STM32W108B-KEXT.pdf
(209 pages)
3.STM32W108B-KEXT.pdf
(27 pages)
4.STM32W108B-KEXT.pdf
(6 pages)
5.STM32W108B-SK.pdf
(21 pages)
6.STM32W108B-KEXT.pdf
(14 pages)
7.STM32W108B-KEXT.pdf
(36 pages)
Specifications of STM32W108B-SK
Featured Product
STM32 Cortex-M3 Companion Products
Contents
Board
Silicon Manufacturer
ST Micro
Core Architecture
ARM
Core Sub-architecture
Cortex - M3
Silicon Core Number
STM32
Silicon Family Name
STM32W108xx
Kit Contents
Board
Features
IEEE
Mfg Application Notes
STM32W108 Adjacent Channel Rejection Measurements
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- STM32W108B-KEXT PDF datasheet
- STM32W108B-KEXT PDF datasheet #2
- STM32W108B-KEXT PDF datasheet #3
- STM32W108B-KEXT PDF datasheet #4
- STM32W108B-SK PDF datasheet #5
- STM32W108B-KEXT PDF datasheet #6
- STM32W108B-KEXT PDF datasheet #7
- Current page: 189 of 209
- Download datasheet (3Mb)
STM32W108CB, STM32W108HB
Table 45
a sampling rate of 6 MHz. ADC_HVSELP and ADC_HVSELN are programmed to 0 to
disable the input buffer. The single-ended measurements were done at f
0 dBFS level (where full-scale is a 1.2 V p-p swing). The differential measurements were
done at f
common mode voltage of 0.6 V.
Table 45.
1. INL and DNL are referenced to a LSB of the Equivalent ADC Bits shown in the last row of
ADC_PERIOD
Conversion Time (µs)
Nyquist Freq (kHz)
3 dB Cut-off (kHz)
INL (codes peak)
INL (codes RMS)
DNL (codes peak)
DNL (codes RMS)
ENOB (from single-cycle test)
SNR (dB)
SINAD (dB)
SDFR (dB)
THD (dB)
ENOB (from SNR)
ENOB (from SINAD)
Equivalent ADC Bits
Single-Ended
Differential
Single-Ended
Differential
Single-Ended
Differential
Single-Ended
Differential
Single-Ended
Differential
Single-Ended
Differential
(effective number of bits) can be calculated from either SNR (signal to non-harmonic noise ratio) or SINAD
(signal-to-noise and distortion ratio).
input
describes the key ADC parameters measured at 25°C and VDD_PADS at 3.0 V, for
Parameter
ADC module key parameters for input buffer disabled
and 6 MHz sampling
= 7.7% f
Nyquist
; -6 dBFS level (where full-scale is a 2.4 V p-p swing) and a
Doc ID 16252 Rev 8
[15:11]
0.084
0.046
0.026
0.007
5.33
93.8
56.6
5.6
-45
-45
5.6
5.6
5.5
5.6
35
35
35
35
60
60
0
5
(1)
[15:10]
0.084
0.044
0.023
0.009
10.7
46.9
28.3
7.0
-54
-54
7.1
7.1
7.0
7.1
44
44
44
44
68
69
1
6
0.076
0.044
0.013
[15:9]
21.3
23.4
14.1
0.15
-63
-63
8.5
8.6
8.6
8.5
8.6
53
53
53
53
75
77
2
7
Performance
0.274
0.147
0.052
0.015
[15:8]
42.7
11.7
7.07
10.0
10.0
10.1
10.1
-68
-71
9.9
62
62
62
62
75
80
3
8
0.518
0.292
0.096
0.024
[15:7]
85.3
5.86
3.54
11.4
11.4
11.5
11.0
11.4
-70
-76
70
71
68
70
75
80
Electrical characteristics
4
9
1.057
0.119
[15:6]
2.93
1.77
0.58
0.03
12.6
12.1
12.5
11.4
12.4
171
input
-70
-77
75
77
71
75
75
80
10
5
Table
= 7.7% f
2.106
0.196
[15:5]
0.884
1.47
1.14
0.05
13.1
12.4
12.9
11.5
12.8
341
-70
-78
76
79
71
77
75
80
11
45. ENOB
6
189/209
Nyquist
4.174
2.352
0.371
0.082
0.732
0.442
[15:4]
13.2
12.5
13.0
11.5
13.0
683
-70
-78
77
80
71
77
75
80
12
7
;
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