SAF-XC164CS-32F40F BB-A Infineon Technologies, SAF-XC164CS-32F40F BB-A Datasheet - Page 65

• Manufacturer Part Number: SAF-XC164CS-32F40F BB-A
• Description: IC MCU 16BIT 256KB FLSH 100TQFP
• Manufacturer: Infineon Technologies
• Series: XC16xr

Specifications of SAF-XC164CS-32F40F BB-A

• Core Processor: C166SV2
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.7 V
• Data Converters: A/D 14x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: 2xASC, 2xSSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 79
• Number Of Timers: 11
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 14 Channel
• Packages: PG-TQFP-100
• Max Clock Frequency: 40.0 MHz
• Sram (incl. Cache): 12.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 14
• Program Memory: 256.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.4
4.4.1
The internal operation of the XC164CS is controlled by the internal master clock
The master clock signal
different mechanisms. The duration of master clock periods (TCMs) and their variation
(and also the derived external timing) depend on the used mechanism to generate
This influence must be regarded when calculating the timings for the XC164CS.
Figure 15
Note: The example for PLL operation shown in
The used mechanism to generate the master clock is selected by register PLLCON.
Data Sheet
the example for prescaler operation refers to a divider factor of 2:1.
Phase Locked Loop Operation (1:N)
f
f
Direct Clock Drive (1:1)
f
f
Prescaler Operation (N:1)
f
f
OSC
MC
OSC
MC
OSC
MC
AC Parameters
Definition of Internal Timing
Generation Mechanisms for the Master Clock
f
MC
can be generated from the oscillator clock signal
63
Figure 15
refers to a PLL factor of 1:4,
TCM
Electrical Parameters
TCM
TCM
MCT05555
Derivatives
V1.1, 2006-08
XC164-32
f
OSC
f
MC
f
.
MC
via
.