SAF-XC164CS-32F40F BB-A Infineon Technologies, SAF-XC164CS-32F40F BB-A Datasheet - Page 11

• Manufacturer Part Number: SAF-XC164CS-32F40F BB-A
• Description: IC MCU 16BIT 256KB FLSH 100TQFP
• Manufacturer: Infineon Technologies
• Series: XC16xr

Specifications of SAF-XC164CS-32F40F BB-A

• Core Processor: C166SV2
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.7 V
• Data Converters: A/D 14x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: 2xASC, 2xSSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 79
• Number Of Timers: 11
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 14 Channel
• Packages: PG-TQFP-100
• Max Clock Frequency: 40.0 MHz
• Sram (incl. Cache): 12.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 14
• Program Memory: 256.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Table 2
Sym-
bol
RSTIN
P20.12 2
NMI
P0H.0 -
P0H.3
Data Sheet
Pin
Num.
1
3
4 … 7
Pin Definitions and Functions
Input
Outp.
I
IO
I
IO
Function
Reset Input with Schmitt-Trigger characteristics. A low level
at this pin while the oscillator is running resets the XC164CS.
A spike filter suppresses input pulses < 10 ns. Input pulses
> 100 ns safely pass the filter. The minimum duration for a
safe recognition should be 100 ns + 2 CPU clock cycles.
Note: The reset duration must be sufficient to let the
For details, please refer to the description of P20.
Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the XC164CS into power
down mode. If NMI is high, when PWRDN is executed, the
part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
For details, please refer to the description of PORT0.
hardware configuration signals settle.
External circuitry must guarantee low level at the
RSTIN pin at least until both power supply voltages
have reached the operating range.
9
General Device Information
Derivatives
V1.1, 2006-08
XC164-32