SAF-XC164CS-32F40F BB-A Infineon Technologies, SAF-XC164CS-32F40F BB-A Datasheet - Page 25

• Manufacturer Part Number: SAF-XC164CS-32F40F BB-A
• Description: IC MCU 16BIT 256KB FLSH 100TQFP
• Manufacturer: Infineon Technologies
• Series: XC16xr

Specifications of SAF-XC164CS-32F40F BB-A

• Core Processor: C166SV2
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.7 V
• Data Converters: A/D 14x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: 2xASC, 2xSSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 79
• Number Of Timers: 11
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 14 Channel
• Packages: PG-TQFP-100
• Max Clock Frequency: 40.0 MHz
• Sram (incl. Cache): 12.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 14
• Program Memory: 256.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.4
With an interrupt response time of typically 8 CPU clocks (in case of internal program
execution), the XC164CS is capable of reacting very fast to the occurrence of non-
deterministic events.
The architecture of the XC164CS supports several mechanisms for fast and flexible
response to service requests that can be generated from various sources internal or
external to the microcontroller. Any of these interrupt requests can be programmed to
being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).
In contrast to a standard interrupt service where the current program execution is
suspended and a branch to the interrupt vector table is performed, just one cycle is
‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a
single byte or word data transfer between any two memory locations with an additional
increment of either the PEC source, or the destination pointer, or both. An individual PEC
transfer counter is implicitly decremented for each PEC service except when performing
in the continuous transfer mode. When this counter reaches zero, a standard interrupt is
performed to the corresponding source related vector location. PEC services are very
well suited, for example, for supporting the transmission or reception of blocks of data.
The XC164CS has 8 PEC channels each of which offers such fast interrupt-driven data
transfer capabilities.
A separate control register which contains an interrupt request flag, an interrupt enable
flag and an interrupt priority bitfield exists for each of the possible interrupt nodes. Via its
related register, each node can be programmed to one of sixteen interrupt priority levels.
Once having been accepted by the CPU, an interrupt service can only be interrupted by
a higher prioritized service request. For the standard interrupt processing, each of the
possible interrupt nodes has a dedicated vector location.
Fast external interrupt inputs are provided to service external interrupts with high
precision requirements. These fast interrupt inputs feature programmable edge
detection (rising edge, falling edge, or both edges).
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with
an individual trap (interrupt) number.
Table 4
hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.
Note: Interrupt nodes which are not assigned to peripherals (unassigned nodes), may
Data Sheet
be used to generate software controlled interrupt requests by setting the
respective interrupt request bit (xIR).
shows all of the possible XC164CS interrupt sources and the corresponding
Interrupt System
23
Functional Description
Derivatives
V1.1, 2006-08
XC164-32