SAF-XC164CS-32F40F BB-A Infineon Technologies, SAF-XC164CS-32F40F BB-A Datasheet - Page 13

• Manufacturer Part Number: SAF-XC164CS-32F40F BB-A
• Description: IC MCU 16BIT 256KB FLSH 100TQFP
• Manufacturer: Infineon Technologies
• Series: XC16xr

Specifications of SAF-XC164CS-32F40F BB-A

• Core Processor: C166SV2
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.7 V
• Data Converters: A/D 14x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: 2xASC, 2xSSC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 79
• Number Of Timers: 11
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 14 Channel
• Packages: PG-TQFP-100
• Max Clock Frequency: 40.0 MHz
• Sram (incl. Cache): 12.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 14
• Program Memory: 256.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Table 2
Sym-
bol
TRST
P3
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
P3.11
P3.12
P3.13
P3.15
Data Sheet
Pin
Num.
36
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Pin Definitions and Functions (cont’d)
Input
Outp.
I
IO
O
I/O
I
I
I
I
O
O
I
I
I
O
O
I
I
I
I/O
I/O
O
I
I/O
I
O
O
I
I/O
I
O
O
Function
the XC164CS’s debug system. For normal system operation,
pin TRST should be held low.
Port 3 is a 14-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance
state) or output (configurable as push/pull or open drain
driver). The input threshold of Port 3 is selectable (standard
or special).
The following Port 3 pins also serve for alternate functions:
T6OUT
RxD1
EX1IN
TCK
CAPIN
TDI
T3OUT
TDO
T3EUD
TMS
T4IN
TxD1
BRKOUT
T3IN
T2IN
BRKIN
MRST0
MTSR0
TxD0
EX2IN
RxD0
EX2IN
BHE
WRH
EX3IN
SCLK0
EX3IN
CLKOUT
FOUT
Test-System Reset Input. A high level at this pin activates
GPT2 Timer T6 Toggle Latch Output,
ASC1 Data Input (Async.) or Inp./Outp. (Sync.),
Fast External Interrupt 1 Input (alternate pin A),
Debug System: JTAG Clock Input
GPT2 Register CAPREL Capture Input,
Debug System: JTAG Data In
GPT1 Timer T3 Toggle Latch Output,
Debug System: JTAG Data Out
GPT1 Timer T3 External Up/Down Control Input,
Debug System: JTAG Test Mode Selection
GPT1 Timer T4 Count/Gate/Reload/Capture In.,
ASC0 Clock/Data Output (Async./Sync.),
Debug System: Break Out
GPT1 Timer T3 Count/Gate Input
GPT1 Timer T2 Count/Gate/Reload/Capture In.,
Debug System: Break In
SSC0 Master-Receive/Slave-Transmit In/Out.
SSC0 Master-Transmit/Slave-Receive Out/In.
ASC0 Clock/Data Output (Async./Sync.),
Fast External Interrupt 2 Input (alternate pin B)
ASC0 Data Input (Async.) or Inp./Outp. (Sync.),
Fast External Interrupt 2 Input (alternate pin A)
External Memory High Byte Enable Signal,
External Memory High Byte Write Strobe,
Fast External Interrupt 3 Input (alternate pin B)
SSC0 Master Clock Output / Slave Clock Input,
Fast External Interrupt 3 Input (alternate pin A)
System Clock Output (= CPU Clock),
Programmable Frequency Output
11
General Device Information
Derivatives
V1.1, 2006-08
XC164-32