UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 542

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.4.13 Reception error
the reception error interrupt request signal (INTCB0RE) is generated when the next receive operation is completed
before the CB0RX register is read after the reception end interrupt request signal (INTCB0R) is generated, and the
overrun error flag (CB0STR.CB0OVE) is set to 1.
if a reception error has occurred, the INTCB0RE signal is generated again upon the next reception completion if the
CB0RX register is not read.
the next receive data from the INTCB0R signal generation.
540
INTCB0RE signal
SIB0 pin capture
When transfer is performed with reception enabled (CB0CTL0.CB0RXE bit = 1) in the continuous transfer mode,
Even if an overrun error has occurred, the previous receive data is lost since the CB0RX register is updated. Even
To avoid an overrun error, complete reading the CB0RX register until one half clock before sampling the last bit of
(1) Operation timing
INTCB0R signal
(1) Start continuous transfer.
(2) Completion of the first transfer
(3) The CB0RX register cannot be read until one half clock before the completion of the second transfer.
(4) An overrun error occurs, and the reception error interrupt request signal (INTCB0RE) is generated. The
CB0RX register
CB0RX register
Shift register
CB0OVE bit
read signal
SCKB0 pin
receive data is overwritten.
SIB0 pin
timing
(1)
CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
01H
02H
05H 0AH 15H 2AH 55H AAH 00H 01H 02H 05H 0AH 15H 2AH 55H
User’s Manual U17716EJ2V0UD
(2)
AAH
(3)
(4)
55H