UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 469

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.9 Notes on Operation
11.9.1 Stopping conversion operation
the conversion results are not stored in A/Dn conversion result register m (ADAnCRm).
generated in all modes.
11.9.2 Timer/external trigger interval
the total number of conversion clocks specified by the ADAnM1.ADAnFR1 and ADAnM1.ADAnFR0 bits (see Table
11-2 Number of Conversion Clocks).
11.9.3 Operation in standby mode
When the ADAnM0.ADAnCE bit is cleared to 0 during a conversion operation, the conversion operation stops and
The ADAnCE bit is not cleared to 0 even after the A/Dn conversion end interrupt request signal (INTADn) has been
Remark
Make sure that the occurrence interval of the trigger in timer trigger mode or external trigger mode is longer than
(1) When 0 < trigger occurrence interval < total number of A/D conversion clocks
(2) When trigger occurrence interval ≥ total number of A/D conversion clocks
(1) HALT mode
(2) IDLE mode, STOP mode
When the timer/external trigger is input during a conversion operation, the conversion operation is aborted and
the conversion starts according to the last timer/external trigger input.
When conversion operations are aborted, the conversion results from the conversion operation immediately
before are not stored in the ADAnCRm register. Note, therefore, that the generation of the INTADn signal and
storing of the result in the ADAnCRm register are not guaranteed.
Remark
The INTADn signal is generated, and the value at the end of conversion is correctly stored in the ADAnCRm
register. Design so that the trigger occurrence interval is equal or greater than the total number of A/D
conversion clocks.
Remark
In this mode, A/D conversion continues.
As clock supply to A/D converters 0 and 1 is stopped, no conversion operations are performed.
When these modes are released by the maskable interrupt request signal input pin
ADAnM2, and ADAnS registers and A/Dn conversion result register m (ADAnCRm) hold their values.
However, when the IDLE or STOP mode is set during a conversion operation, the conversion operation is
suspended. At this time, if the mode released by the maskable interrupt request signal input pin
conversion operation resumes. At this time, the A/Dn conversion end interrupt request signal (INTADn) may
be generated, but the conversion result written to the ADAnCRm register will be undefined.
Note INTP0 to INTP5
Remark
n = 0, 1, m = 0 to 3
n = 0, 1, m = 0 to 3
n = 0, 1, m = 0 to 3
n = 0, 1, m = 0 to 3
CHAPTER 11 A/D CONVERTERS 0 AND 1
User’s Manual U17716EJ2V0UD
Note
, the ADAnM0, ADAnM1,
Note
, the
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