UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 245

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(3) CCR1 buffer register
(4) CCR2 buffer register
(5) CCR3 buffer register
(6) Edge detector
(7) Output controller
(8) Selector
This is a 16-bit compare register that compares the count value of the 16-bit counter.
When the TQnCCR1 register is used as a compare register, the value written to the TQnCCR1 register is
transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches the value of the
CCR1 buffer register, a compare match interrupt request signal (INTTQnCC1) is generated.
The CCR1 buffer register cannot be read or written directly.
The TQnCCR1 register is cleared to 0000H after reset, and the CCR1 buffer register is cleared to 0000H.
This is a 16-bit compare register that compares the count value of the 16-bit counter.
When the TQnCCR2 register is used as a compare register, the value written to the TQnCCR2 register is
transferred to the CCR2 buffer register. When the count value of the 16-bit counter matches the value of the
CCR2 buffer register, a compare match interrupt request signal (INTTQnCC2) is generated.
The CCR2 buffer register cannot be read or written directly.
The TQnCCR2 register is cleared to 0000H after reset, and the CCR2 buffer register is cleared to 0000H.
This is a 16-bit compare register that compares the count value of the 16-bit counter.
When the TQnCCR3 register is used as a compare register, the value written to the TQnCCR3 register is
transferred to the CCR3 buffer register. When the count value of the 16-bit counter matches the value of the
CCR3 buffer register, a compare match interrupt request signal (INTTQnCC3) is generated.
The CCR3 buffer register cannot be read or written directly.
The TQnCCR3 register is cleared to 0000H after reset, and the CCR3 buffer register is cleared to 0000H.
This circuit detects the valid edges input to the TIQ00 to TIQ03 and EVTQ0 pins. No edge, rising edge, falling
edge, or both the rising and falling edges can be selected as the valid edge by using the TQ0IOC1 and
TQ0IOC2 registers.
This circuit controls the output of the TOQ00, TOQ01/TOQH01, TOQ02, TOQ03/TOQH02, TOQH03, and
TOQ10 pins. The output of the TOQ00, TOQ01/TOQH01, TOQ02, TOQ03/TOQH02, and TOQH03 pins is
controlled by the TQ0IOC0 register. The output of the TOQ10 pin is controlled by the TQ1IOC0 register.
This selector selects the count clock for the 16-bit counter. Eight types of internal clocks or an external event
can be selected as the count clock.
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ)
User’s Manual U17716EJ2V0UD
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