UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 227

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(b) Pulse width measurement with capture register
When pulse width measurement is performed with the TPkCCRa register used as a capture register,
software processing is necessary for reading the capture register each time the INTTPkCCa signal has
been detected and for calculating an interval.
When executing pulse width measurement in the free-running timer mode, two pulse widths can be
measured with one channel.
To measure a pulse width, the pulse width can be calculated by reading the value of the TPkCCRa register
in synchronization with the INTTPkCCa signal, and calculating the difference between the read value and
the previously read value.
Remark
INTTPkCC0 signal
INTTPkCC1 signal
TPkCCR0 register
TPkCCR1 register
INTTPkOV signal
TIPk0 pin input
TIPk1 pin input
16-bit counter
TPkOVF bit
TPkCE bit
k = 0, 2
a = 0, 1
FFFFH
0000H
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
0000H
Pulse interval
0000H
Pulse interval
(D
User’s Manual U17716EJ2V0UD
D
00
(D
)
D
00
10
10
)
Pulse interval
(10000H +
D
D
01
Cleared to 0 by
CLR instruction
Pulse interval
00
- D
(10000H +
D
D
00
11
)
01
D
− D
D
10
Pulse interval
11
10
(D
)
02
− D
D
D
Pulse interval
02
01
01
(10000H +
D
)
D
12
Cleared to 0 by
CLR instruction
11
− D
Pulse interval
(10000H +
D
D
03
11
12
D
)
− D
D
02
03
02
)
Pulse interval
(10000H +
D
13
Pulse interval
(10000H +
− D
D
04
D
D
D
Cleared to 0 by
CLR instruction
− D
12
12
03
13
)
03
)
D
04
D
D
04
13
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