UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 501

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.7 Cautions
register retaining the value it had immediately before the clock supply was stopped. The TXDAn pin output also holds
and outputs the value it had immediately before the clock supply was stopped. However, the operation is not
guaranteed after the clock supply is resumed. Therefore, after the clock supply is resumed, the circuits should be
initialized by setting the UAnCTL0.UAnPWR, UAnCTL0.UAnRXE, and UAnCTL0.UAnTXE bits to 000.
(8) Transfer rate during continuous transmission
When the clock supply to UARTAn is stopped (for example, in IDLE1 or STOP mode), the operation stops with each
Remark
During continuous transmission, the transfer rate from the stop bit to the next start bit is usually 2 base clocks
longer. However, timing initialization is performed via start bit detection by the receiving side, so this has no
influence on the transfer result.
Assuming 1 bit data length: FL; stop bit length: FLstp; and base clock frequency: f
equation.
Therefore, the transfer rate during continuous transmission is as follows.
FLstp = FL + 2/f
Transfer rate = 11 × FL + (2/f
n = 0, 1
Start bit
FL
Bit 0
CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
Figure 12-11. Transfer Rate During Continuous Transmission
UCLK
FL
Bit 1
FL
UCLK
1 data frame
)
User’s Manual U17716EJ2V0UD
Bit 7
FL
Parity bit
FL
Stop bit
FLstp
Start bit
FL
UCLK
Start bit of 2nd byte
, we obtain the following
Bit 0
FL
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