UPD78F9221CS-CAC-A Renesas Electronics America, UPD78F9221CS-CAC-A Datasheet - Page 86

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UPD78F9221CS-CAC-A

Manufacturer Part Number
UPD78F9221CS-CAC-A
Description
MCU 8BIT 2KB FLASH 20PIN
Manufacturer
Renesas Electronics America
Series
78K0S/Kx1+r
Datasheet

Specifications of UPD78F9221CS-CAC-A

Core Processor
78K0S
Core Size
8-Bit
Speed
10MHz
Connectivity
LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
84
Remark PCC:
Note Operation stop time is 277 s (MIN.), 544 s (TYP.), and 1.075 ms (MAX.).
(a) The internal reset signal is generated by the power-on-clear function on power application, the option byte is
(b) The option byte is referenced and the system clock is selected. Then the external clock operates as the
referenced after reset, and the system clock is selected.
system clock.
System clock
Internal reset
CPU clock
PPCC: Preprocessor clock control register
RESET
V
DD
Figure 5-13. Status Transition of Default Start by External Clock Input
Processor clock control register
H
Figure 5-12. Timing of Default Start by External Clock Input
Interrupt
(a)
HALT
System clock is selected.
CHAPTER 5 CLOCK GENERATORS
(Operation stops
selected by option byte
Option byte is read.
External clock input
Clock division ratio
instruction
variable during
power-on-clear
CPU operation
HALT
User’s Manual U16898EJ6V0UD
Reset by
application
Power
V
Start with PCC = 02H,
PPCC = 02H
Note
instruction
DD
STOP
)
> 2.1 V (TYP.)
(b)
STOP
Interrupt
PCC = 02H, PPCC = 02H
Reset signal
External clock input

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