UPD78F9221CS-CAC-A Renesas Electronics America, UPD78F9221CS-CAC-A Datasheet - Page 400

• Manufacturer Part Number: UPD78F9221CS-CAC-A
• Description: MCU 8BIT 2KB FLASH 20PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9221CS-CAC-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

398
Serial
interface
UART6
Interrupt
functions
Standby
function
Function
Permissible
baud rate range
during
reception
Vector table
address
IF0, IF1:
Interrupt
request flag
registers,
MK0, MK1:
Interrupt mask
flag registers
INTM0:
External
interrupt mode
register 0
INTM1:
External
interrupt mode
register 1
Interrupt
requests are
held pending
Interrupt
request
pending
STOP mode
STOP mode,
HALT mode
STOP mode
OSTS:
Oscillation
stabilization
time select
register
Details of
Function
Make sure that the baud rate error during reception is within the permissible
error range, by using the calculation expression shown below.
No interrupt sources correspond to the vector table address 0014H.
Because P30, P31, P41, and P43 have an alternate function as external
interrupt inputs, when the output level is changed by specifying the output mode
of the port function, an interrupt request flag is set. Therefore, the interrupt
mask flag should be set to 1 before using the output mode.
Be sure to clear bits 0 and 1 to 0.
Before setting the INTM0 register, be sure to set the corresponding interrupt
mask flag (
clear the interrupt request flag (
(
Be sure to clear bits 2 to 7 to 0.
Before setting INTM1, set PMK3 to 1 to disable interrupts.
To enable interrupts, clear PIF3 to 0, then clear PMK3 to 0.
Interrupt requests will be held pending while the interrupt request flag registers
(IF0, IF1) or interrupt mask flag registers (MK0, MK1) are being accessed.
Multiple interrupts can be acknowledged even for low-priority interrupts.
The LSRSTOP setting is valid only when “Can be stopped by software” is set for
the low-speed internal oscillator by the option byte.
When shifting to the STOP mode, be sure to stop the peripheral hardware
operation before executing STOP instruction (except the peripheral hardware
that operates on the low-speed internal oscillation clock).
The following sequence is recommended for operating current reduction of the
A/D converter when the standby function is used: First clear bit 7 (ADCS) and
bit 0 (ADCE) of the A/D converter mode register (ADM) to 0 to stop the A/D
conversion operation, and then execute the HALT or STOP instruction.
If the low-speed internal oscillator is operating before the STOP mode is set,
oscillation of the low-speed internal oscillation clock cannot be stopped in the
STOP mode (refer to Table 13-1).
To set and then release the STOP mode, set the oscillation stabilization time as
follows. Expected oscillation stabilization time of resonator
stabilization time set by OSTS
MK = 0), which will enable interrupts.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16898EJ6V0UD
MK = 1) to disable interrupts. After setting the INTM0 register,
IF = 0), then clear the interrupt mask flag
Cautions
Oscillation
p. 217
p. 221
pp. 224,
225
p. 226
p. 226
p. 227
p. 227
p. 230
p. 231
p. 233
p. 234
p. 234
p. 234
p. 235
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