UPD78F9221CS-CAC-A Renesas Electronics America, UPD78F9221CS-CAC-A Datasheet - Page 399

• Manufacturer Part Number: UPD78F9221CS-CAC-A
• Description: MCU 8BIT 2KB FLASH 20PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9221CS-CAC-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Serial
interface
UART6
Function
ASICL6:
Asynchronous
serial interface
control register
6
POWER6,
TXE6, and
RXE6: 7, 6, and
5 of ASIM6
UART mode
Parity types
and operation
Continuous
transmission
TXBF6 during
continuous
transmission:
Bit 1 of ASIF6
TXSF6 during
continuous
transmission:
Bit 0 of ASIF6
Normal
reception
Generation of
serial clock
Details of
Function
Before setting the SBRT6 bit to 1, make sure that bit 7 (POWER6) and bit 5
(RXE6) of ASIM6 = 1. Moreover, after setting the SBRT6 bit to 1, do not clear
the SBRT6 bit to 0 before the SBF reception ends (an interrupt request signal is
generated).
The read value of the SBRT6 bit is always 0. SBRT6 is automatically cleared to
0 after SBF reception has been correctly completed.
Before setting the SBTT6 bit to 1, make sure that bit 7 (POWER6) and bit 6
(TXE6) of ASIM6 = 1. Moreover, after setting the SBTT6 bit to 1, do not clear
the SBTT6 bit to 0 before the SBF transmission ends (an interrupt request
signal is generated).
The read value of the SBTT6 bit is always 0. SBTT6 is automatically cleared to
0 at the end of SBF transmission.
Before rewriting the DIR6 and TXDLV6 bits, clear the TXE6 and RXE6 bits to 0. p. 196
Clear POWER6 to 0 after clearing TXE6 and RXE6 to 0 to set the operation
stop mode.
To start the operation, set POWER6 to 1, and then set TXE6 and RXE6 to 1.
Take the relationship with the other party of communication into consideration
for the port mode register and port register setting procedure. In order to avoid
the generation of unintended start bits (falling signals), set PM43 to 0 (output)
after having set P43 to 1.
Fix the PS61 and PS60 bits to 0 when the interface is used for LIN
communication operation.
Use the value of the TXBF flag to judge whether continuous transmission is
possible. Do not write the next transmit data, by making a judgment only by the
fact that the TXSF6 flag has been set to 1.
When the interface is used for LIN communication operation, the continuous
transmission function cannot be used. Make sure that asynchronous serial
interface transmission status register 6 (ASIF6) is 00H before writing transmit
data to transmit buffer register 6 (TXB6).
To transmit data continuously, write the first transmit data (first byte) to the
TXB6 register. Be sure to check that the TXBF6 flag is “0”. If so, write the next
transmit data (second byte) to the TXB6 register. If data is written to the TXB6
register while the TXBF6 flag is “1”, the transmit data cannot be guaranteed.
To initialize the transmission unit upon completion of continuous transmission,
be sure to check that the TXSF6 flag is “0” after generation of the transmission
completion interrupt, and then execute initialization. If initialization is executed
while the TXSF6 flag is “1”, the transmit data cannot be guaranteed.
Be sure to read receive buffer register 6 (RXB6) even if a reception error occurs.
Otherwise, an overrun error will occur when the next data is received, and the
reception error status will persist.
Reception is always performed with the “number of stop bits = 1”. The second
stop bit is ignored.
Be sure to read asynchronous serial interface reception error status register 6
(ASIS6) before reading RXB6.
Keep the baud rate error during transmission to within the permissible error
range at the reception destination.
Make sure that the baud rate error during reception satisfies the range shown in
(4) Permissible baud rate range during reception.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16898EJ6V0UD
Cautions
p. 196
p. 196
p. 196
p. 196
p. 198
p. 199
p. 203
p. 205
p. 205
p. 205
p. 205
p. 209
p. 209
p. 209
p. 215
p. 215
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