UPD78F9221CS-CAC-A Renesas Electronics America, UPD78F9221CS-CAC-A Datasheet - Page 220

• Manufacturer Part Number: UPD78F9221CS-CAC-A
• Description: MCU 8BIT 2KB FLASH 20PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9221CS-CAC-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

218
Therefore, the maximum receivable baud rate at the transmission source is as follows.
Similarly, the maximum permissible data frame length can be calculated as follows.
Therefore, the minimum receivable baud rate at the transmission source is as follows.
The permissible baud rate error between UART6 and the transmission source can be calculated from the above
minimum and maximum baud rate expressions, as follows.
Remarks 1. The permissible error of reception depends on the number of bits in one frame, input clock
10
11
8
20
50
100
255
Minimum permissible data frame length: FLmin = 11
Division Ratio (k)
FLmax = 11
FLmax =
BRmax = (FLmin/11)
BRmin = (FLmax/11)
2. k: Set value of BRGC6
frequency, and division ratio (k). The higher the input clock frequency and the higher the division
ratio (k), the higher the permissible error.
21k – 2
20k
FL
Table 11-5. Maximum/Minimum Permissible Baud Rate Error
FL
k + 2
2
Maximum Permissible Baud Rate Error
k
11
1
1
CHAPTER 11 SERIAL INTERFACE UART6
=
=
FL =
21k + 2
21k
22k
20k
21k
+3.53%
+4.26%
+4.56%
+4.66%
+4.72%
2
User’s Manual U16898EJ6V0UD
2
Brate
Brate
k
2
FL
FL
k
2k
2
Minimum Permissible Baud Rate Error
FL =
21k + 2
2k
3.61%
4.31%
4.58%
4.67%
4.73%
FL