M30835FJGP#U5 Renesas Electronics America, M30835FJGP#U5 Datasheet - Page 323

• Manufacturer Part Number: M30835FJGP#U5
• Description: IC M32C/83 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30835FJGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 121
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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NOTES:
NOTES:
2
Table 21. 20 Pin Settings (3)
Table 21. 21 Pin Settings (4)
Figure 21.39 Transmit and Receive Operation
9 0
Name
P11
P11
P11
Name
P15
P15
P15
. 1
C
Port
Port
1. Set the MOD2 to MOD0 bits in the corresponding register to "111
1. Set the MOD2 to MOD0 bits in the corresponding register to "111
B
1 3
8 /
0
Base timer i
ISCLKi pin output
(transmit clock in the
channel 3 generation
function)
ISTxDi pin output
(data to be transmitted)
SIOiTR bit
when IRS=0
(no data in the
transmit buffer)
SIOiTR bit
when IRS=1
(transmission completed)
ISRxDi pin input
(received data)
SIOiRR bit
The above applies under the following conditions:
0
1
2
0
1
2
function used).
function used).
3
3 0
J
G
• The CKDIR bit in the GiMR register is set to "0" (internal clock)
• The UFORM bit in the GiMR register is be set to "0" (LSB first)
• The IPOL and OPOL bits in the GiCR register are set to "0" (no inverse)
- 4
n a
o r
ISTxD1 output
ISCLK1 input
ISCLK1 output PS5_1 = 1
ISRxD1 input
ISTxD0 output
ISCLK0 input
ISCLK0 output PS9_1 = 1
ISRxD0 input
1 0
3 .
u
, 1
1 3
Function
Function
p
0 2
(
M
6 0
3
2
m
C
n+2
8 /
Page 298
Write to the GiTB register
, 3
PS5 Register PD11 Register IPS Register
PS5_0 = 1
PS5_1 = 0
PS5_2 = 0
PS9 Register PD15 Register IPS Register
PS9_0 = 1
PS9_1 = 0
PS9_2 = 0
M
3
2
C
f o
8 /
Bit 0
Bit 0
4
The base timer is reset by the channel 0
waveform generation function
Write "0" by program
if setting to "0"
3
8 8
) T
Bit and Setting
-
PD11_1 = 0
-
PD11_2 = 0
Bit and Setting
-
PD15_2 = 0
-
PD15_2 = 0
Bit 1
Bit 1
-
IPS1 = 1
-
IPS1 = 1
-
IPS0 = 1
-
IPS0 = 1
21. Intelligent I/O (Group 0, 1 Communication Function)
Bit 2
Bit 2
G1POCR0
-
G1POCR1
-
G0POCR0
-
G0POCR1
-
Register
Register
Bit 6
n : Setting value of the GiPO0 register
m : Setting value of the GiPO3 register
i
SIOiTR bit : Bit in the IIOjIR register (j = 1,3)
SIOiRR bit : Bit in the IIOkIR register (k = 0,2)
IRS bit
Bit 6
Write "0" by program if setting to "0"
: 0,1
2
2
" (output of the communication
" (output of the communication
(1)
(1)
: Bit in the GiMR register
Bit7
Bit 7
Write "0" by program
if setting to "0"