M30835FJGP#U5 Renesas Electronics America, M30835FJGP#U5 Datasheet - Page 153

• Manufacturer Part Number: M30835FJGP#U5
• Description: IC M32C/83 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30835FJGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 121
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
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E
3
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Table 13.2 DMAC II Index Configuration in Transfer Mode
Chained Transfer
Figure 13.3 MOD
End-of-Transfer
Interrupt
2
DMAC II
Index
0
1
9
C
3 .
B
8 /
0
1
3
0
3
J
G
4
a
b15
0 -
n
o r
3 .
Transfer Mode (MOD)
1
u
, 1
3
NOTES:
p
1
Not Used
Not Used
COUNT
2
(
8 bytes
1. MOD must be located on the RAM.
2. When the MULT bit is set to "0" (no multiple transfer), bits 4 to 6 becomes the OPER, BRST, INTE
DADR
SADR
M
MOD
0
bits. When the MULT bit is set to "1" (multiple transfer), bits 4 to 6 becomes the CNT0 to CNT2 bits.
0
3
6
2
b8
C
Memory-to-Memory Transfer
/Immediate Data Transfer
b7
8 /
Page 128
, 3
Not Used
12 bytes
COUNT
CADR0
CADR1
DADR
SADR
Used
MOD
M
3
2
C
f o
b0
8 /
4
Not Used
CNT0
(b14 - b8)
12 bytes
Symbol
CNT1
CNT2
3
OPER/
CHAIN
COUNT
UPDD
8
UPDS
BRST/
MULT
INTE/
SADR
DADR
IADR0
IADR1
SIZE
Used
) T
IMM
MOD
8
Bit
(2)
(1)
(2)
(2)
Transfer Unit
Select Bit
Transfer Data
Select Bit
Transfer Source
Direction Select Bit
Transfer Destination
Direction Select Bit
Calculation Transfer
Function Select Bit
Burst Transfer
Select Bit
End-of-Transfer
Interrupt Select Bit
Chained Transfer
Select Bit
Multiple Transfer
Select Bit
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
16 bytes
COUNT
CADR0
CADR1
SADR
DADR
IADR0
IADR1
Used
Used
Bit Name
MOD
Not Used
Not Used
10 bytes
COUNT
OADR
SADR
DADR
MOD
0: 8 bits
1: 16 bits
0: Immediate data
1: Memory
0: Fixed address
1: Forward address
0: Fixed address
1: Forward address
0: Not used
1: Used
0: Single transfer
1: Burst transfer
0: Interrupt not used
1: Use interrupt
0: Chained transfer not used
1: Use chained transfer
0: Multiple
transfer not used
(MULT=0)
Not Used
Function
14 bytes
COUNT
CADR0
CADR1
OADR
Calculation Transfer
SADR
DADR
Used
MOD
Not Used
COUNT
14 bytes
OADR
SADR
DADR
IADR0
IADR1
Used
MOD
b6 b5 b4
Set to "1"
0 0 0: Do not set
0 0 1: Once
0 1 0: Twice
1 1 0: 6 times
1 1 1: 7 times
1: Use multiple
Set to "0"
transfer
:
:
(MULT=1)
Function
18 bytes
to this value
COUNT
CADR0
CADR1
SADR
DADR
IADR0
IADR1
OADR
MOD
Used
Used
Multiple Transfer
i=1 to 7
Max 32 bytes
(when i=7)
Not Available
Not Available
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
COUNT
SADR1
DADR1
SADRi
DADRi
MOD
13. DMACII