M30835FJGP#U5 Renesas Electronics America, M30835FJGP#U5 Datasheet - Page 302

IC M32C/83 MCU FLASH 144LQFP

M30835FJGP#U5

Manufacturer Part Number
M30835FJGP#U5
Description
IC M32C/83 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30835FJGP#U5

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
144-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Part Number
Manufacturer
Quantity
Price
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Part Number:
M30835FJGP#U5M30835FJGP
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Company:
Part Number:
M30835FJGP#U5M30835FJGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
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Company:
Part Number:
M30835FJGP#U5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
R
R
M
e
E
3
. v
J
2
Figure 21.24 Single-Phase Waveform Output Mode
0
1
C
9
3 .
B
8 /
0
1
3
0
3
J
G
4
a
0 -
n
o r
3 .
1
u
(1) Free-Running Operation
(2) The Base Timer is Reset when the Base Timer Matches the GiPO0 Register
, 1
3
p
1
2
(
(The RST2 to RST0 bits in the GiBCR1 register are set to "000
(The RST1 bit is set to "1", and the RST0 and RST2 bits are set to "0")
NOTES:
The above applies applies under the following conditions:
M
0
0
3
Base Timer i
POijR bit in the
IIOiIR register
OUTCij pin
Base Timer i
OUTCij pin
OUTCij pin
POijR bit in the
IIOiIR register
The above diagram applies under the following conditions:
6
2
2. Waveform output when the INV bit is set to "0" (not inversed) and the IVL bit is set to "1"
1. Waveform output when the INV bit in the GiPOCRj register is set to "0" (not inversed)
• The RST2 to RST0 bits in the GiBCR1 register are set to "000
• The IVL bit in the GiPOCRj register is set to "0" (outputs "L" as default value). The INV
• The UD1 to UD0 bits in the GiBCR1 register are set to "00
• m < n+2
C
(16-bit waveform generation function)
and the IVL bit is set to "0" (output "L" as default value).
(output "H" as default value).
the UD1 to UD0 bits to "00
bit is set to "0" (not inverse).
and the CAS bit to "0" (16-bit waveform generation function)
Page 277
8 /
, 3
M
(1)
(2)
i=0 to 3; j=1 to 7 (however, i=0 when j=1, 4, 5)
m : Setting value of the GiPOj register (0000
n : Setting value of the GiPO0 register (0001
POijR bit: Bits in the IIO0IR to IIO11IR register
i=0 to 3; j=0 to 7 (however, i=0 when j=0, 1, 4, 5)
m : Setting value of the GiPOj register (0000
POijR bit: Bits in the IIO0IR to IIO11IR register
3
2
FFFF
0000
C
f o
0000
8 /
4
16
n+2
"H"
"L"
"H"
"L"
"1"
"0"
"H"
"L"
"1"
"0"
16
3
m
8
m
16
) T
8
f
2
m
BTi
" (counter increment mode), and CAS bit to "0"
f
m
BTi
65536
n+2-m
n+2
f
f
BTi
65536-m
BTi
f
BTi
f
Write "0" by program
if setting to "0"
BTi
Write "0" by
program if
setting to "0"
21. Intelligent I/O (Waveform Generation Function)
16
16
16
2
" (counter increment mode),
to FFFF
to FFFF
to FFFD
2
" (no base timer reset),
16
16
16
)
)
)
2
")

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