M30835FJGP#U5 Renesas Electronics America, M30835FJGP#U5 Datasheet - Page 289

• Manufacturer Part Number: M30835FJGP#U5
• Description: IC M32C/83 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30835FJGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 121
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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21.1 Base Timer
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Table 21.2 Base Timer Specifications
Count Source (f
Counting Operation
Counter Start Condition
Counter Stop Condition
Base Timer Reset Condition
Value when the Base Timer is Reset
Interrupt Request
Read from Base Timer
Write to Base Timer
Selectable Function
The base timer is a free-running counter that counts an internally generated count source.
Table 21.2 lists specifications of the base timer. Figures 21.5 to 21.9 show registers associated with the
base timer. Figure 21.16 shows a block diagram of the base timer. Figure 21.17 shows an example of a
cascaded connection. Figure 21.18 shows an example of the base timer in counter increment mode. Figure
21.19 shows an example of the base timer in counter increment/decrement mode. Figure 21.20 shows an
example of two-phase pulse signal processing mode.
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two-phase pulse input divided by
The base timer increments the counter
The base timer increments/decrements the counter
Two-phase pulse signal processing
• When starting the base timer of each group separately, set the BTS bit in
the GiBCR1 register to "1" (base timer starts counting)
• When starting the base timer of multiple groups simultaneously, set the
Set the BTiS bit in the BTSR register to "0" (base timer reset) and the BTS
bit in the GiBCR1 register to "0" (base timer reset)
• Synchronized with the base timer reset in different groups:
• Matching values in the base timer and GiPO0 register
• "L" signal applied to the external interrupt pin
• Reset request from communication function (Group 2 and 3)
"0000
The BTiR bit in the interrupt request register is set to "1" (interrupt requested)
when bit 14 or bit 15 in the base timer overflows (See Figure 10.14.)
• The GiBT register indicates counter value while the base timer is running
• The GiBT register is indeterminate when the base timer is reset
When a value is written while the base timer is running, the counter
immediately starts counting from this value. No value can be written while
the base timer is reset.
• Cascaded connection (Group 0 and 1)
• Counter increment/decrement mode (Group 0 and 1)
1
BTiS bit in the BTSR register to "1" (base timer starts counting)
Group0 : synchronized with group 1 base timer reset
Group1 : synchronized with group 0 base timer reset
Group2 : synchronized with group 1 base timer reset
Group3 : synchronized with group 2 base timer reset
Group 0 : INT0 pin
Group 1 : INT1 pin
Group 1 base timer is incremented every time bit 15 in the group 0 base
timer overflows (See Figure 21.17)
The base timer starts when the BTS bit or the BTiS bit is set to "1". After
incrementing to "FFFF
"0000
is reset by matching with the GiPO0 register), the counter decrements after
the base timer matches the GiPO0 register. The base timer increments the
counter again when the counter becomes "0000
divided by
n
n
: determined by the DIV4 to DIV0 bits in the GiBCR0 register
=0 to 31; however no division when
16
"
16
". If the RST1 bit in the GiBCR1 register is set to "1" (the base timer
________
________
2(n+1)
(Group 0 to 3),
16
", the counter is then decremented back to
2(n+1)
Specification
(Group 0 and 1)
n
=31
21. Intelligent I/O (Base Timer)
16.
" (See Figure 21.19.)