M30835FJGP#U5 Renesas Electronics America, M30835FJGP#U5 Datasheet - Page 214

• Manufacturer Part Number: M30835FJGP#U5
• Description: IC M32C/83 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30835FJGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 121
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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3
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Table 16.7 Registers to be Used and Settings in UART
2
0
NOTES:
Table 16.7 lists registers to be used and settings. Tables 16.8 to 16.10 list pin settings. When UARTi (i=0
to 4) operation mode is selected, the TxDi pin outputs an "H" signal before transfer is started (the TxDi pin
is in a high-impedance state when the N-channel open drain output is selected). Figure 16.14 shows an
example of a transmit operation in UART mode. Figure 16.15 shows an example of a receive operation in
UART mode.
UiTB
UiRB
UiBRG
UiMR
UiC0
UiC1
UiSMR
UiSMR2
UiSMR3
UiSMR4
1
C
9
Register
3 .
B
1. Use bits 0 to 6 when transfer data is 7 bits long, bits 0 to 7 when 8 bits long, bits 0 to 8 when 9 bits long.
8 /
0
1
3
0
3
J
G
4
a
0 -
n
o r
3 .
1
u
, 1
3
p
1
0 to 8
0 to 8
OER, FER,
PER, SUM
0 to 7
SMD2 to SMD0
CKDIR
STPS
PRY, PRYE
IOPOL
CLK0, CLK1
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
TE
TI
RE
RI
UiIRS
UiRRM
UiLCH
UiERE
0 to 7
0 to 7
0 to 7
0 to 7
2
(
M
0
0
3
6
2
Bit
C
Page 189
8 /
, 3
M
3
2
C
f o
8 /
Set transmit data
Received data can be read
Error flags
Set bit rate
Set to "100
Set to "101
Set to "110
Select the internal clock or external clock
Select stop bit length
Select parity enable or disable, odd or even
Select TxD / RxD I/O polarity
Select count source for the UiBRG register
Select either CTS or RTS when using either
Transfer register empty flag
Enables or disables the CTS or RTS function
Select output format of the TxDi pin
Set to "0"
Select the LSB first or MSB first when a transfer data is 8 bits long
Set to "0" when transfer data is 7 bits or 9 bits long
Set to "1" to enable data transmission
Transfer buffer empty flag
Set to "1" to enable data reception
Reception complete flag
Select how the UARTi transmit interrupt is generated
Set to "0"
Select whether or not data logic is inversed when transfer data length is 7 or
8 bits. Set to "0" when transfer data length is 9 bits.
Set to either "0" or "1"
Set to "00
Set to "00
Set to "00
Set to "00
4
3
8
) T
8
16
16
16
16
2
2
2
"
"
"
"
" when transfer data is 7 bits long
" when transfer data is 8 bits long
" when transfer data is 9 bits long
_______
(1)
_______
________
(1)
Function
_______
16. Serial I/O (UART)