DF2552BR26DV Renesas Electronics America, DF2552BR26DV Datasheet - Page 37

• Manufacturer Part Number: DF2552BR26DV
• Description: IC H8S/2552 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2552BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 I
Figure 14.1 Block Diagram of I
Figure 14.2 External Circuit Connections of I/O Pins................................................................ 478
Figure 14.3 I
Figure 14.4 I
Figure 14.5 Master Transmit Mode Operation Timing (1)......................................................... 494
Figure 14.6 Master Transmit Mode Operation Timing (2)......................................................... 494
Figure 14.7 Master Receive Mode Operation Timing (1) .......................................................... 496
Figure 14.8 Master Receive Mode Operation Timing (2) .......................................................... 497
Figure 14.9 Slave Transmit Mode Operation Timing (1) ........................................................... 498
Figure 14.10 Slave Transmit Mode Operation Timing (2) ........................................................... 499
Figure 14.11 Slave Receive Mode Operation Timing (1)............................................................. 500
Figure 14.12 Slave Receive Mode Operation Timing (2)............................................................. 501
Figure 14.13 Clocked Synchronous Serial Transfer Format......................................................... 501
Figure 14.14 Transmit Mode Operation Timing .......................................................................... 502
Figure 14.15 Receive Mode Operation Timing ............................................................................ 503
Figure 14.16 Block Diagram of Noise Canceler........................................................................... 504
Figure 14.17 Sample Flowchart for Master Transmit Mode ........................................................ 505
Figure 14.18 Sample Flowchart for Master Receive Mode .......................................................... 506
Figure 14.19 Sample Flowchart for Slave Transmit Mode........................................................... 507
Figure 14.20 Sample Flowchart for Slave Receive Mode ............................................................ 508
Figure 14.21 The Timing of the Bit Synchronous Circuit ............................................................ 510
Section 15 A/D Converter
Figure 15.1 Block Diagram of A/D Converter ........................................................................... 514
Figure 15.2 Access to ADDR (When Reading H'AA40) ........................................................... 521
Figure 15.3 A/D Conversion Timing (Single-Chip Mode, Channel 1 Selected) ........................ 523
Figure 15.4 A/D Conversion Timing (Scan Mode, Channels AN0 to AN2 Selected)................ 524
Figure 15.5 A/D Conversion Timing.......................................................................................... 525
Figure 15.6 External Trigger Input Timing ................................................................................ 526
Figure 15.7 A/D Conversion Accuracy Definitions ................................................................... 528
Figure 15.8 A/D Conversion Accuracy Definitions ................................................................... 528
Figure 15.9 Example of Analog Input Circuit ............................................................................ 530
Figure 15.10 Example of Analog Input Protection Circuit........................................................... 531
Figure 15.11 Analog Input Pin Equivalent Circuit ....................................................................... 532
Section 16 D/A Converter
Figure 16.1 Block Diagram of D/A Converter ........................................................................... 533
Figure 16.2 D/A Converter Operation Example ......................................................................... 537
2
C Bus Interface 2 (IIC2)
2
2
C Bus Formats ...................................................................................................... 492
C Bus Timing........................................................................................................ 492
2
C Bus Interface 2..................................................................... 477
Rev. 6.00 Sep. 24, 2009 Page xxxv of xlvi
REJ09B0099-0600