DF2552BR26DV Renesas Electronics America, DF2552BR26DV Datasheet - Page 618
![IC H8S/2552 MCU FLASH 176-LFBGA](/photos/28/61/286115/176-lfbga_sml.jpg)
DF2552BR26DV
Manufacturer Part Number
DF2552BR26DV
Description
IC H8S/2552 MCU FLASH 176-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2500r
Specifications of DF2552BR26DV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
26MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
104
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
176-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2552BR26DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 17 IEBus™ Controller (IEB) [H8S/2552 Group]
17.3.14 IEBus Receive Buffer Register (IERBR)
IERBR is a 1-byte read-only buffer that stores data received in master or slave reception. This
register can be read when the RxRDY flag in IERSR is set to 1. This register indicates the data
field value both in master and slave receptions. This register cannot be modified.
Figure 17.7 shows the relationship between transmission signal format and registers in IEBus data
reception.
Rev. 6.00 Sep. 24, 2009 Page 570 of 928
REJ09B0099-0600
Bit
7
6
5
4
3
2
1
0
Bit Name
RBR7
RBR6
RBR5
RBR4
RBR3
RBR2
RBR1
RBR0
[In slave reception]
Communications frame
Register
[In master reception]
Communications frame
Register settings
Figure 17.7 Relationship between Transmission Signal Format and Registers
Initial Value
0
0
0
0
0
0
0
0
Note: * Received slave address is compared with IEAR1 and IEAR2. If they match,
Master address
Master address
IEMA1, IEMA2 IEAR1, IEAR2
IEAR1, IEAR2 IESA1, IESA2
the following operations are performed.
in IEBus Data Reception
R/W
R
R
R
R
R
R
R
R
Slave address
Slave address
(*)
Description
One-byte read-only buffer that stores data
received in master or slave reception
CTL3 to CTL0
Control bits
Control bits
IERCTL
in IEMCR
Message length
Message length
IERBFL
IERBFL
bits
bits
Data bits
Data bits
IERBR
IERBR
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