DF2552BR26DV Renesas Electronics America, DF2552BR26DV Datasheet - Page 535
DF2552BR26DV
Manufacturer Part Number
DF2552BR26DV
Description
IC H8S/2552 MCU FLASH 176-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2500r
Specifications of DF2552BR26DV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
26MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
104
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
176-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
DF2552BR26DV
Manufacturer:
Renesas Electronics America
Quantity:
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Bit
4
3
2
1
0
Bit Name
NAKIE
STIE
ACKE
ACKBR
ACKBT
Initial
Value
0
0
0
0
0
R/W
R/W
R/W
R/W
R
R/W
Stop Condition Detection Interrupt Enable
Description
NACK Receive Interrupt Enable
This bit enables or disables the NACK receive interrupt
request (NAKI) and the overrun error (setting of the OVE
bit in ICSR) interrupt request (ERI) with the clocked
synchronous format, when the NACKF and AL bits in ICSR
are set to 1. NAKI can be canceled by clearing the NACKF,
OVE, or NAKIE bit to 0.
0: NACK receive interrupt request (NAKI) is disabled.
1: NACK receive interrupt request (NAKI) is enabled.
0: Stop condition detection interrupt request (STPI) is
1: Stop condition detection interrupt request (STPI) is
Acknowledge Bit Judgement Select
0: The value of the receive acknowledge bit is ignored, and
1: If the receive acknowledge bit is 1, continuous transfer is
Receive Acknowledge
In transmit mode, this bit stores the acknowledge data that
are returned by the receive device. This bit cannot be
modified.
0: Receive acknowledge = 0
1: Receive acknowledge = 1
Transmit Acknowledge
In receive mode, this bit specifies the bit to be sent at the
acknowledge timing.
0: 0 is sent at the acknowledge timing.
1: 1 is sent at the acknowledge timing.
disabled.
enabled.
continuous transfer is performed.
halted.
Rev. 6.00 Sep. 24, 2009 Page 487 of 928
Section 14 I
2
C Bus Interface 2 (IIC2)
REJ09B0099-0600
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