HD64F3048F16 Renesas Electronics America, HD64F3048F16 Datasheet - Page 893

• Manufacturer Part Number: HD64F3048F16
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048F16

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

D.2
Reset in T1 State
Figure D.1 is a timing diagram for the case in which RES goes low during the T1 state of an
external memory access cycle. As soon as RES goes low, all ports are initialized to the input state.
AS, RD, HWR, and LWR go high, and the data bus goes to the high-impedance state. The address
bus is initialized to the low output level 0.5 state after the low level of RES is sampled. Sampling
of RES takes place at the fall of the system clock ( ).
RES
Internal
reset signal
Address bus
CS
CS
AS
RD (read access)
HWR, LWR
(write access)
Data bus
(write access)
I/O port
0
7
Pin States at Reset
to CS
Figure D.1 Reset during Memory Access (Reset during T1 State)
1
High
High
High
Access to external address
T1
T2
Rev. 3.00 Sep 27, 2006 page 865 of 872
T3
H'000000
Appendix D Pin States
High-impedance
High-impedance
High-impedance
REJ09B0325-0300