HD64F3048F16 Renesas Electronics America, HD64F3048F16 Datasheet - Page 12

• Manufacturer Part Number: HD64F3048F16
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048F16

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Rev. 3.00 Sep 27, 2006 page x of xxvi
Item
5.5.4 Usage Notes on
External Interrupts
Figure 5.9 IRQnF
Flag When Interrupt
Processing Is Not
Conducted
10.2.3 Timer Mode
Register (TMDR)
Bit 6—Phase Counting
Mode Flag (MDF)
13.2.8 Bit Rate
Register (BRR)
Table 13.3 Examples
of Bit Rates and BRR
Settings in
Asynchronous Mode
13.3.2 Operation in
Asynchronous Mode
Figure 13.8 Example
of SCI Receive
Operation (8-Bit Data
with Parity and One
Stop Bit)
Page
120
335
473,
475
492
Revision (See Manual for Details)
Figure amended
IRQaF
IRQbF
Table amended
Table amended
Figure amended
RDRF
FER
Counting Direction
TCLKA pin
TCLKB pin
Bit Rate
(bits/s)
110
150
300
600
1200
2400
4800
9600
19200
31250
38400
1
n
1
1
1
0
0
0
0
0
0
0
0
Start
bit
0
Occurrence condition 1
N
212
155
77
155
77
38
19
9
4
2
1
D0
3
Down-Counting
Low
D1
Error
(%)
0.03
0.16
0.16
0.16
0.16
0.16
–2.34
–2.34
–2.34
0.00
22.07
Read
Read
1 frame
1
1
Data
Write
Write
High
D7
0
1
Execution
n
2
1
1
0
0
0
0
0
0
0
0
Parity
bit
IRQb
0/1
High
N
64
191
95
191
95
47
23
11
5
3
2
3.6864
Stop
bit
(MHz)
1
RXI
request
Start
bit
Error
(%)
0.70
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
–7.84
0.00
Low
0
RXI interrupt handler
reads data in RDR and
clears RDRF flag to 0
D0
Up-Counting
High
n
3
3
2
2
1
1
0
0
0
0
0
D1
Data
N
110
80
162
80
162
80
162
80
40
24
19
Low
25
Occurrence condition 2
D7
Error
(%)
–0.02
0.47
–0.15
0.47
–0.15
0.47
–0.15
0.47
–0.76
0.00
1.73
Read
Clear in error
Parity
bit
Read
0/1
0
1
Low
Framing error,
ERI request
Stop
bit
Write
Write
1
0
0
Idle (mark)
state
High
1