HD64F3048F16 Renesas Electronics America, HD64F3048F16 Datasheet - Page 371

• Manufacturer Part Number: HD64F3048F16
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048F16

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

TCNT can be cleared to H'0000 by compare match with GRA or GRB or by input capture to GRA
or GRB (counter clearing function) in the same channel.
When TCNT overflows (changes from H'FFFF to H'0000), the OVF flag is set to 1 in TSR of the
corresponding channel.
When TCNT underflows (changes from H'0000 to H'FFFF), the OVF flag is set to 1 in TSR of the
corresponding channel.
The TCNTs are linked to the CPU by an internal 16-bit bus and can be written or read by either
word access or byte access.
Each TCNT is initialized to H'0000 by a reset and in standby mode.
10.2.8
The general registers are 16-bit registers. The ITU has 10 general registers, two in each channel.
Channel
0
1
2
3
4
A general register is a 16-bit readable/writable register that can function as either an output
compare register or an input capture register. The function is selected by settings in TIOR.
When a general register is used as an output compare register, its value is constantly compared
with the TCNT value. When the two values match (compare match), the IMFA or IMFB flag is set
to 1 in TSR. Compare match output can be selected in TIOR.
When a general register is used as an input capture register, rising edges, falling edges, or both
edges of an external input capture signal are detected and the current TCNT value is stored in the
Bit
Initial value
Read/Write
General Registers A, B (GRA, GRB)
Abbreviation
GRA0, GRB0
GRA1, GRB1
GRA2, GRB2
GRA3, GRB3
GRA4, GRB4
R/W
15
1
R/W
14
1
R/W
13
1
R/W
12
1
Function
Output compare/input capture register
Output compare/input capture register; can be buffered by
buffer registers BRA and BRB
R/W
11
1
R/W
10
1
R/W
9
1
R/W
Section 10 16-Bit Integrated Timer Unit (ITU)
8
1
R/W
Rev. 3.00 Sep 27, 2006 page 343 of 872
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
REJ09B0325-0300
R/W
2
1
R/W
1
1
R/W
0
1