HD64F3048F16 Renesas Electronics America, HD64F3048F16 Datasheet - Page 388

• Manufacturer Part Number: HD64F3048F16
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048F16

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 10 16-Bit Integrated Timer Unit (ITU)
1. Set bits TPSC2 to TPSC0 in TCR to select the counter clock source. If an external clock source
2. For periodic counting, set CCLR1 and CCLR0 in TCR to have TCNT cleared at GRA compare
3. Set TIOR to select the output compare function of GRA or GRB, whichever was selected in
4. Write the count period in GRA or GRB, whichever was selected in step 2.
5. Set the STR bit to 1 in TSTR to start the timer counter.
Free-running and periodic counter operation: A reset leaves the counters (TCNTs) in ITU
channels 0 to 4 all set as free-running counters. A free-running counter starts counting up when the
corresponding bit in TSTR is set to 1. When the count overflows from H'FFFF to H'0000, the
OVF flag is set to 1 in TSR. If the corresponding OVIE bit is set to 1 in TIER, a CPU interrupt is
requested. After the overflow, the counter continues counting up from H'0000. Figure 10.15
illustrates free-running counting.
When a channel is set to have its counter cleared by compare match, in that channel TCNT
operates as a periodic counter. Select the output compare function of GRA or GRB, set bit CCLR1
or CCLR0 in TCR to have the counter cleared by compare match, and set the count period in GRA
or GRB. After these settings, the counter starts counting up as a periodic counter when the
corresponding bit is set to 1 in TSTR. When the count matches GRA or GRB, the IMFA or IMFB
flag is set to 1 in TSR and the counter is cleared to H'0000. If the corresponding IMIEA or IMIEB
bit is set to 1 in TIER, a CPU interrupt is requested at this time. After the compare match, TCNT
continues counting up from H'0000. Figure 10.16 illustrates periodic counting.
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is selected, set bits CKEG1 and CKEG0 in TCR to select the desired edge(s) of the external
clock signal.
match or GRB compare match.
step 2.
H'FFFF
H'0000
STR0 to
STR4 bit
OVF
TCNT value
Figure 10.15 Free-Running Counter Operation
Time