HD64F3048F16 Renesas Electronics America, HD64F3048F16 Datasheet - Page 233

• Manufacturer Part Number: HD64F3048F16
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048F16

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

8.2
In short address mode, transfers can be carried out independently on channels A and B. Short
address mode is selected by bits DTS2A and DTS1A in data transfer control register A (DTCRA)
as indicated in table 8.4.
Table 8.4
Channel
0
1
8.2.1
A memory address register (MAR) is a 32-bit readable/writable register that specifies a source or
destination address. The transfer direction is determined automatically from the activation source.
An MAR consists of four 8-bit registers designated MARR, MARE, MARH, and MARL. All bits
of MARR are reserved: they cannot be modified and are always read as 1.
An MAR functions as a source or destination address register depending on how the DMAC is
activated: as a destination address register if activation is by a receive-data-full interrupt from the
serial communication interface (SCI) (channel 0), and as a source address register otherwise.
Bit
Initial value
Read/Write
Register Descriptions (Short Address Mode)
Memory Address Registers (MAR)
31
1
Bit 2:
DTS2A
1
Other than above
1
Other than above
30
1
Selection of Short and Full Address Modes
29
1
MARR
28
1
27
1
26
1
Bit 1:
DTS1A
1
1
25
1
24
1
R/W
23
R/W
22
R/W
Description
DMAC channel 0 operates as one channel in full address
mode
DMAC channels 0A and 0B operate as two independent
channels in short address mode
DMAC channel 1 operates as one channel in full address
mode
DMAC channels 1A and 1B operate as two independent
channels in short address mode
21
R/W
MARE
20
Source or destination address
R/W
19
R/W
18
R/W
17
Undetermined
R/W
16
R/W
15
R/W
14
Rev. 3.00 Sep 27, 2006 page 205 of 872
R/W
13
R/W
MARH
12
R/W
11
R/W
10
R/W
9
Section 8 DMA Controller
R/W
8
R/W
7
R/W
6
REJ09B0325-0300
R/W
5
R/W
MARL
4
R/W
3
R/W
2
R/W
1
R/W
0